JEDEC Solid State Technology Association announced the publication of JEP200: Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices. Developed jointly by JEDEC’s JC-70.1 Gallium Nitride and JC-70.2 Silicon Carbide Subcommittees, JEP200 is available for free download from the JEDEC website.
Proliferation of soft switching power conversion topologies brought about the need to accurately quantify the energy stored in a power device’s output capacitance because the energy impacts efficiency of power converters. JEP200, developed in collaboration with academia, addresses the critical power supply industry need to properly test and measure the switching energy loss due to the output capacitance hysteresis in semiconductor power devices and details tests circuits, measurement methods, and data extraction algorithms. The document applies not only to wide bandgap power semiconductors such as GaN and SiC, but also silicon power transistors and diodes.
“Professionals in high-frequency power conversion systems have long sought a standardized approach to testing new switching energy losses,” said Dr. Jaume Roig, Member of Technical Staff, onsemi and Vice Chair of the JC-70 Committee. “This document now provides helpful guidance on testing energy losses related to output capacitance hysteresis caused by displacement currents. With this clarity, system optimization can proceed more accurately.”
“JEDEC’s JC-70 committee has the expertise necessary to meet the demands of the entire power semiconductor industry, and the development of JEP200 demonstrates how the JEDEC process enabled the committee to swiftly respond to an industry need,” said John Kelly, JEDEC President. “JEP200 encompasses GaN, SiC, and Si power devices, helping the industry navigate design challenges caused by the growing number of new power conversion topologies.”
Original – JEDEC
