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JEDEC Solid State Technology Association announced the publication of JEP200: Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices. Developed jointly by JEDEC’s JC-70.1 Gallium Nitride and JC-70.2 Silicon Carbide Subcommittees, JEP200 is available for free download from the JEDEC website.
Proliferation of soft switching power conversion topologies brought about the need to accurately quantify the energy stored in a power device’s output capacitance because the energy impacts efficiency of power converters. JEP200, developed in collaboration with academia, addresses the critical power supply industry need to properly test and measure the switching energy loss due to the output capacitance hysteresis in semiconductor power devices and details tests circuits, measurement methods, and data extraction algorithms. The document applies not only to wide bandgap power semiconductors such as GaN and SiC, but also silicon power transistors and diodes.
“Professionals in high-frequency power conversion systems have long sought a standardized approach to testing new switching energy losses,” said Dr. Jaume Roig, Member of Technical Staff, onsemi and Vice Chair of the JC-70 Committee. “This document now provides helpful guidance on testing energy losses related to output capacitance hysteresis caused by displacement currents. With this clarity, system optimization can proceed more accurately.”
“JEDEC’s JC-70 committee has the expertise necessary to meet the demands of the entire power semiconductor industry, and the development of JEP200 demonstrates how the JEDEC process enabled the committee to swiftly respond to an industry need,” said John Kelly, JEDEC President. “JEP200 encompasses GaN, SiC, and Si power devices, helping the industry navigate design challenges caused by the growing number of new power conversion topologies.”
Original – JEDEC
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JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announced that it is hosting an Automotive Electronics Forum on September 19, 2024 in San Jose, CA. There is no charge to attend, but advance registration is required and space is limited.
The Forum offers an impressive lineup of influential speakers covering a diverse range of innovative topics related to automotive electronics, including keynote presentations from Ford Motor Company, Micron, Rivian, Samsung, SK Hynix, and STMicroelectronics. Speakers from Infineon, Keysight, MIPI, Monolithic Power Systems, Synopsys, TI, VisIC Technologies and Wolley round out the agenda. There’s something for everyone looking to stay ahead in this dynamic field.
Mian Quddus, Chairman of the JEDEC Board of Directors, said: “We are delighted to invite industry professionals to join us and gain inspiration from the leading companies that are shaping the future of automotive technology.” He added, “Supporting the industry through educational outreach is an integral part of JEDEC’s mission, and we look forward to welcoming attendees to the JEDEC Automotive Electronics Forum next month.”
Original – JEDEC
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JEDEC Solid State Technology Association announced that its JC-15 Committee for Thermal Characterization Techniques for Semiconductor Packages welcomes interested companies to join JEDEC and participate in committee meetings and activities.
Near-term plans for the committee include the evolution of standards that cover the provision of electronic thermal models in neutral file formats (e.g. JEP181, JEP30 T101), as well as the review and improvement of several key standards previously developed by the committee. For more information about JC-15 activities and JEDEC membership visit the JEDEC website.
Activities within JC-15’s scope include the standardization of thermal characterization techniques, both testing and modeling, for electronic packages, components, and materials for semiconductor devices.
“The activities of JC-15 reflect JEDEC’s commitment to evolving alongside the dynamic microelectronics industry,” said Robin Bornoff, Acting Chair of the JC-15 Committee. He added, “The wide range of subjects covered by JC-15 standards provides our members with diverse opportunities to contribute their knowledge and expertise to further enhance the efficacy of the electronics thermal supply chain.”
Original – JEDEC
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JEDEC Solid State Technology Association announced the publication of JEP198: Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices. Developed by JEDEC’s JC-70.1 Gallium Nitride Subcommittee, JEP198 is available for free download from the JEDEC website.
JEP198 presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power transistors. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions, and cascode GaN power transistors.
This publication covers suggested stress conditions and related test parameters for evaluating the TDB reliability of GaN power transistors using the off-state bias. The stress conditions and test parameters for both High Temperature Reverse Bias Stress and Application Specific Stress-Testing are designed to evaluate the reliability of GaN transistors over their useful lifetime under accelerated stress conditions.
“We are becoming more dependent on power electronics in all facets of our daily lives. As such, the technologies behind those systems are advancing and so too must the device-specific qualification processes. The new GaN-focused Guideline for Reverse Bias Reliability Evaluation is a critical step toward achieving that goal,” said Ron Barr, VP of Quality and Reliability, Transphorm and Co-Chair of the Task Group 701_1.
“This was a collaborative effort conducted by both GaN semiconductor and end product manufacturers. I’m proud of the work the task group delivered. It is an important framework to ensure cross-industry uniformity that will, in the end, provide power system manufacturers the necessary confidence when designing with GaN devices.”
“With the rise of renewable energy and electrification of our lives, the efficiency of power semiconductors is becoming more critical. This is where GaN power semiconductors have proven to be a valuable technology. The Guideline for Reverse Bias Reliability Evaluation is another step in improving confidence in GaN Technology and the products that are on and being brought to market,” said Dr. Kurt Smith, VP of Reliability and Qualification at VisIC Technologies and Chair of JC-70.1.
“This document was developed through collaboration of the multi-corporation team of industry experts to represent the best practices for evaluating GaN devices. It was a long multi-year process to reach consensus and the team is to be commended for the quality document and all of the hard work that went into it.”
Original – JEDEC
