MOSFET Tag Archive

  • Vishay Intertechnology Introduced a New 80 V Symmetric Dual N-Nhannel Power MOSFET

    Vishay Intertechnology Introduced a New 80 V Symmetric Dual N-Channel Power MOSFET

    2 Min Read

    Vishay Intertechnology, Inc. introduced a new 80 V symmetric dual n-channel power MOSFET that combines high and low side TrenchFET® Gen IV MOSFETs in a single 3.3 mm by 3.3 mm PowerPAIR® 3x3FS package. For power conversion in industrial and telecom applications, the Vishay Siliconix SiZF4800LDT increases power density and efficiency, while enhancing thermal performance, reducing component counts, and simplifying designs.

    This dual MOSFET can be used in place of two discrete devices typically specified in the PowerPAK 1212 package — saving 50 % board space. The device provides designers with a space-saving solution for synchronous buck converters, point of load (POL) converters, and half- and full-bridge power stages for DC/DC converters in radio base stations, industrial motor drives, welding equipment, and power tools. In these applications, the high and low side MOSFETs of the SiZF4800LDT form an optimized combination for 50 % duty cycles, while its logic level turn-on at 4.5 V simplifies circuit driving.

    To increase power density, the MOSFET offers best in class on-resistance down to 18.5 mW typical at 4.5 V. This is 16 % lower than the closest competing device in the same package dimensions. For increased efficiency in high frequency switching applications, the SiZF4800LDT offers a low on-resistance times gate charge — a key figure of merit (FOM) for MOSFETs used in power conversion applications — of 131mW*nC and on-resistance times gain-drain charge

    The device’s flip-chip technology enhances thermal dissipation — resulting in 54 % lower thermal resistance compared to competing MOSFETs. The SiZF4800LDT’s combination of low on-resistance and thermal resistance results in a continuous drain current of 36 A, which is 38 % higher than the closest competing device. The MOSFET features a unique pin configuration that enables a simplified PCB layout and supports shortened switching loops to minimize parasitic inductance. The SiZF4800LDT is 100 % Rg- and UIS-tested, RoHS-compliant, and halogen-free.

    Competitor Comparison Table:

    Part numberSiZF4800LDT (New)CompetitorSiZF4800LDTPerformance improved
    PackagePowerPAIR 3x3FSPowerPAIR 3x3FS 
    Dimensions (mm)3.3 x 3.3 x 0.753.3 x 3.3 x 0.75
    ConfigurationSymmetric dualSymmetric dual
    VDS (V)8080
    VGS (V)± 20± 20
    RDS(on) (mΩ) @ 4.5 VGSTyp.18.522+16 %
    Max.23.829+18 %
    Qg (nC) @ 4.5 VGSTyp.7.16.0
    FOM131132+1 %
    ID (A)Max.3626+38 %
    RthJC (C/W)Max.2.24.8+54 %

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  • Nexperia Released New 40V and 100V MOSFETs

    Nexperia Released New 40V and 100V MOSFETs

    3 Min Read

    Nexperia is once again bringing its product innovations to APEC and today announced the release of several new MOSFETs to further broaden its range of discrete switching solutions for use in various applications across multiple end markets.

    This release includes 100 V application specific MOSFETs (ASFETs) for PoE, eFuse and relay replacement in 60% smaller DFN2020 packaging, and 40 V NextPowerS3 MOSFETs with improved electromagnetic compatibility (EMC) performance.

    PoE switches typically have up to 48 ports, each requiring 2 MOSFETs for protection. With up to 96 MOSFETs on a single PCB, any reduction in device footprint is attractive. For this reason, Nexperia has released 100 V PoE ASFETs in 2 mm x 2 mm DFN2020 packaging which occupies 60% less space than previous versions in LFPAK33 packaging.

    A critical function of these devices is to protect PoE ports by limiting inrush currents while safely managing fault conditions. To manage this scenario, Nexperia has enhanced the safe operating area (SOA) of these devices by up to 3x with only a minimal increase in RDS(on).  These ASFETs are also suitable for battery management, Wi-Fi hotspot, 5G picocell and CCTV applications and can serve as replacements for mechanical relays in smart thermostats, for example.

    EMC-related issues caused by MOSFET switching usually only emerge late in the product development life cycle and resolving them can incur additional R&D costs and delay market release. Typical solutions include using significantly more expensive MOSFETs with lower RDS(on) (to slow down switching and absorb excessive voltage ringing) or to fit an external capacitive snubber circuit but this approach has the disadvantage of increasing component count.

    Nexperia has optimized its 40 V NextPowerS3 MOSFETs to offer similar EMC performance as that which can be achieved using an external snubber circuit, while also offering higher efficiency. These MOSFETs are suitable for use in switching converters and motor controllers across various applications and are available in LFPAK56 packaging.

    “By introducing these latest additions to our range of discrete FET solutions at APEC 2024, Nexperia showcases how we leverage our expertise in R&D to deliver optimized solutions. Both our new 100 V PoE ASFETs as well as improved EMC performance in our 40 V NextPowerS3 MOSFETs demonstrate our commitment to supporting engineers in overcoming challenges across diverse applications. These innovations underscore Nexperia’s dedication to providing efficient, compact, and reliable solutions that empower our customers to succeed in today’s ever-evolving market,” says Chris Boyce, MOSFET Marketing & Product Group Director at Nexperia.

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  • Infineon Technologies Adds 750V G1 Discrete MOSFET to CoolSiC™ Family

    Infineon Technologies Adds 750V G1 Discrete MOSFET to CoolSiC™ Family

    2 Min Read

    Infineon Technologies AG introduced the 750V G1 discrete CoolSiC™ MOSFET to meet the increasing demand for higher efficiency and power density in industrial and automotive power applications. The product family includes both industrial-graded and automotive-graded SiC MOSFETs that are optimized for totem-pole PFC, T-type, LLC/CLLC, dual active bridge (DAB), HERIC, buck/boost, and phase-shifted full bridge (PSFB) topologies.

    The MOSFETs are ideal for use in both typical industrial applications, such as electric vehicle charging, industrial drives, solar and energy storage systems, solid state circuit breaker, UPS systems, servers/ datacenters, telecom, and in the automotive sector, such as onboard chargers (OBC), DC-DC converters, and many more.

    The CoolSiC MOSFET 750 V G1 technology features excellent RDS (on) x Q fr and superior  RDS (on) x Q oss Figure-of-Merits (FOMs), resulting in ultra-high efficiency in hard-switching and soft-switching topologies respectively. Its unique combination of high threshold voltage (V GS(th), Typ. of 4.3 V) with low Q GD/Q GS ratio ensures high robustness against parasitic turn-on and enables unipolar gate driving, leading to increased power density and low cost of the systems.

    All devices use Infineon’s proprietary die-attach technology which delivers outstanding thermal impedance for equivalent die sizes. The highly reliable gate oxide design combined with Infineon’s qualification standards delivers robust and long-term performance.

    With a granular portfolio ranging from 8 to 140 mΩ RDS (on) at 25°C, this new CoolSiC MOSFET 750 V G1 product family meets a wide range of needs. Its design ensures lower conduction and switching losses, boosting overall system efficiency.

    Its innovative packages minimize thermal resistance, facilitate improved heat dissipation, and optimize in-circuit power loop inductance, thereby resulting in high power density and reduced system costs. It’s important to note that this product family features the cutting-edge QDPAK top-side cooled package.

    Original – Infineon Technologies

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  • Infineon Technologies Introduced Dual-Phase Power Modules for AI Data Centers

    Infineon Technologies Introduced Dual-Phase Power Modules for AI Data Centers

    2 Min Read

    Artificial Intelligence is currently driving an exponential increase in global data generation, and consequently increasing the energy demands of the chips supporting this data growth. Infineon Technologies AG launched its TDM2254xD series dual-phase power modules that enable best-in-class power density, quality and total cost of ownership (TCO) for AI data centers.

    The TDM2254xD series products blend innovation in robust OptiMOS TM MOSFET technology with novel packaging and proprietary magnetic structure to deliver industry-leading electrical and thermal performance with robust mechanical design. This lets data centers operate at higher efficiency to meet the high power demands of AI GPU (Graphic Processor Unit) platforms while also significantly reducing TCO.

    Given that AI servers require 3 times more energy than traditional servers, and data centers already consume more than 2 percent of the global energy supply, it is essential to find innovative power solutions and architecture designs that further drive decarbonization. Paving the way for the green AI factory, Infineon’s TDM2254xD dual-phase power modules combine with XDP TM Controller technology to enable efficient voltage regulation for high-performance computing platforms with superior electrical, thermal and mechanical operation.

    Infineon introduced the TDM2254xD series at the Applied Power Electronics Conference (APEC). The modules’ unique design allows for efficient heat transfer from the power stage on to the heat sink through novel inductor design that is optimized to transfer current and heat, thereby allowing for a 2 percent higher efficiency than industry average modules at full load. Improving power efficiency at the core of a GPU yields significant energy savings at scale. This translates into megawatts saved for data centers computing generative AI and in turn leads to reduced CO 2 emissions and millions of dollars in operating cost savings over the system’s lifetime.

    “This unique Product-to-System solution combined with our cutting-edge manufacturing lets Infineon deliver solutions with differentiated performance and quality at scale, thereby significantly reducing total cost of ownership for our customers,” said Athar Zaidi, Senior Vice President, Power & Sensor Systems at Infineon Technologies. “We are excited to bring this solution to market; it will accelerate computing performance and will further drive our mission of digitalization and decarbonization.” 

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  • Toshiba Released Two New Power MOSFETs with High-Speed Diodes

    Toshiba Released Two New Power MOSFETs with High-Speed Diodes

    2 Min Read

    Toshiba Electronic Devices & Storage Corporation has added DTMOSVI(HSD), power MOSFETs with high-speed diodes suitable for switching power supplies, including data centers and photovoltaic power conditioners, to its latest-generation DTMOSVI series with a super junction structure. Shipments of the first two products “TK042N65Z5” and “TK095N65Z5,” 650V N-channel power MOSFETs in TO-247 packages, start today.

    The new products use high-speed diodes to improve the reverse recovery characteristics important for bridge circuit and inverter circuit applications. Against the standard DTMOSVI, they achieve a 65% reduction in reverse recovery time (trr), and an 88% reduction in reverse recovery charge (Qrr) (measurement conditions: -dIDR/dt= 100A/μs).

    The DTMOSVI(HSD) process used in the new products improves on the reverse recovery characteristics of Toshiba’s DTMOSIV series with high-speed diodes (DTMOSIV(HSD)), and has a lower drain cut-off current at high temperatures. The figure of merit “drain-source On-resistance × gate-drain charges” is also lower. The high temperature drain cut-off current of TK042N65Z5 is approximately 90% lower, and the drain-source On-resistance × gate-drain charge 72% lower, than in Toshiba’s current TK62N60W5.

    This advance will cut equipment power loss and help to improve efficiency. The TK042N65Z5 shows a maximum improvement in power supply efficiency over the current TK62N60W5 of about 0.4%, as measured in a 1.5kW LLC circuit.

    A reference design, “1.6 kW Server Power Supply (Upgraded)”, that uses TK095N65Z5 is available on Toshiba’s website today. The company also offers tools that support circuit design for switching power supplies. Alongside the G0 SPICE model, which verifies circuit function in a short time, highly accurate G2 SPICE models that accurately reproduce transient characteristics are now available.

    Toshiba plans to expand the DTMOSVI(HSD) line-up with the release of devices in TO-220 and TO-220SIS through-hole packages, and TOLL and DFN 8×8 surface-mount packages.

    The company also will continue to expand its line-up of the DTMOSVI series beyond the already released 650V and 600V products and the new products with high-speed diodes. This will enhance switching power supply efficiency, contributing to energy-saving equipment.

    Original – Toshiba

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  • Guideline for Reproducible SiC MOSFET Thermal Characterization Based on Source-Drain Voltage

    Guideline for Reproducible SiC MOSFET Thermal Characterization Based on Source-Drain Voltage

    18 Min Read

    Abstract

    This paper aims to provide a guideline with respect to a reproducible thermal transient measurement for SiC MOSFETs. Although the thermal transient measurement based on sourcedrain voltage is a widely applied method for characterizing the thermal properties of MOSFETs, the approach developed for silicon-based devices may not be directly applicable to SiC devices. Therefore, this paper investigates the thermal transient measurement method for SiC MOSFETs using the source-drain voltage as the temperature-sensitive electrical parameter.

    A comprehensive investigation of its linearity, sensitivity, and stability toward yielding the thermal structure-property of the device has been carried out. The investigation includes two primary characterization procedures: temperature calibration and cooling curve measurement. The associated key testing conditions, such as gate voltages, sensing and heating currents, etc., are covered. The study examines the impact of these conditions on both static and dynamic performance to provide a better understanding of the reproducible thermal transient measurement for SiC MOSFETs.

    I. Introduction

    Silicon carbide (SiC) MOSFETs are becoming increasingly popular in a wide range of applications, such as electric vehicles, industrial drives, and high-voltage transmissions. SiC offers several advantages over silicon, including lower power losses at higher switching frequencies, higher operating temperatures, and withstanding higher voltages. However, to ensure safe operation and maximize the device’s lifetime, all these superior performances must be achieved within the maximum junction temperature limit. Therefore, thermal characterization of SiC MOSFETs is essential to define the boundaries.

    Thermal transient measurement is a widely accepted method to characterize the thermal properties of silicon (Si) power semiconductor devices. It has been recognized in several standards, such as JEDEC JESD 51-1 and JEDEC 51-14 and successfully applied to different applications over the past two decades, such as generating RC thermal models for electro-thermal simulation, packaging defect inspection, and junction-to-case thermal resistance measurement.

    However, directly applying this approach to SiC MOSFETs is still doubtful to some extent. For instance, SiC MOSFETs do not have a pn junction in the forward direction and have low on-state resistance, which imposes challenges to measure transient thermal response by the channel voltage. Meanwhile, trapped charge carriers in the gate region may cause second-level electrical disturbances and inevitably affect the extraction of thermal transient from the coupled electrical disturbance. In the state-of-the-art, the source-drain voltage is one of the most used temperature sensitivity electrical parameters (TSEP) for SiC MOSFETs.

    As shown in Fig. 1, the characterization consists of two major procedures, namely temperature calibration and cooling curve measurement. Improper selection of test conditions may result in misleading results. First, calibrating SiC MOSFETs for thermal transient measurement involves selecting the appropriate sensing current and gate voltage as step 1 shown in Fig. 1. While a sensing current of 1/1000 of the nominal current is commonly used for Si devices, it is however still under debate for SiC MOSFETs. Some studies use a small current below 1/1000 of the nominal current, while others suggest a much higher sensing current.

    Fig. 1. Circuit diagram of the thermal transient measurement for SiC MOSFETs

    Additionally, selecting the appropriate negative gate voltage is critical for fully turning off the MOSFET channel and allowing all injected sensing current to flow through the body diode. However, the methodology for selecting the optimal gate voltage value and its impact on the transient thermal impedance remains unclear. It is worth noting that previous studies have mainly focused on steady-state calibration results, but transient temperature measurement requires consideration of transient behaviors, which has not been fully addressed in the literature. In addition to the calibration procedure, the cooling curve measurement of SiC MOSFETs involves other parameters such as heating currents and the switching transient of the gate state.

    Previous studies have mainly focused on power cycling, where only the maximum and minimum temperature points are required. However, the investigation of thermal transient measurement with respect to the temperature dynamics across multiple time scales is limited. Electrical disturbances that occur at any point in time may lead to inaccurate thermal structure properties. Therefore, further investigation of the cooling curve measurement is also crucial. This paper comprehensively investigates the thermal transient measurement approach of SiC MOSFETs using Vsd as the TSEP and focuses on how to obtain more reproducible thermal structural information. Comparing to a preliminary conference version, the contributions of this article are three folds:

    • Evaluated the impact of key testing conditions, including the gate turn-off voltage and sensing current, on the calibration based on static and dynamic tests. Three criteria are proposed to quantify the sensing current and two methods are proposed to justify the gate voltage.
    • Investigated how various parameters affect cooling curve measurement in terms of static and dynamic responses.
    • Derived a guideline of how to perform a reproducible thermal transient measurement of SiC MOSFETs with a proper selection of testing conditions and parameters.

    II. Thermal Transient Measurement

    Fig.1 illustrates the two major steps to perform the thermal transient measurement for a SiC MOSFET, namely, the temperature calibration and cooling curve measurement. The calibration is to obtain the relationship between the TSEP and the device temperature, which is controlled by an external system (e.g., an oven, a dielectric bath, or a temperature-controlled cooling plate). The MOSFET body diode pn junction voltage Vsd shows a linear temperature dependence given a small sensing current going through the device. By measuring Vsd under various temperatures, the relation of Vsd = f(T) can be calibrated.

    Note that a low enough negative gate voltage has to be applied to completely shut the MOSFET channel off during this process (see Fig.2). In the second step, cooling curve measurement is carried out based on two current levels: one is the heating current (Iheat) to heat the device up, and the other is the sensing current for temperature monitoring with a negligible self-heating impact, as shown in Fig. 1 (Step 2).

    Fig. 2. Structure of a SiC MOSFET

    Once Vsd is measured, the inversely calibrated T = f−1 (Vsd) in step 1 converts the measured voltage into the temperature. However, the temperature calibration is developed based on static conditions but the cooling curve is derived from dynamic voltage responses. The compatibility of the two steps has a prerequisite that the electrical disturbance is short and negligible. However, reference pointed out that SiC MOSFETs have much longer electrical disturbance compared to Si devices. Its impacts on thermal transient measurement are not fully understood and will be investigated in the following two sections.

    III. Calibration: Impact of Sensing Current

    To obtain reliable thermal transient measurement for SiC MOSFETs, the sensing current needs to be carefully selected to achieve good linearity, sensitivity, and low power dissipation. Additionally, to minimize unwanted electrical disturbances, a short sensing current pulse is preferable. In this section, three criteria are proposed to quantify the impacts of sensing current.

    A. Impact of Sensing Current Density on Static Performance

    1) Linearity: pn-junction voltage Vpn is used as TSEP due to its linear temperature dependence, which is given by

    E 1

    where Eg is band gap, q is the elementary charge, kb is Boltzmann constant, and A is a device-specific factor. These parameters are either independent of or have weak dependence on temperature. When a constant sensing current density jsense is applied, Vpn varies linearly with temperature T. However, for SiC MOSFETs, the voltage drops across the drift region, contact, and metallization can contribute significantly to Vsd when a high sensing current is used.

    Fig. 3. Calibration curves for multiple sensing currents

    Moreover, at high temperatures and low current densities, the negative temperature coefficient of body diode results in a smaller Vpn. All above phenomenon can jeopardize the linear temperature dependence of Vsd and needs to be properly dealt. Fig. 3(a) shows the calibration results for different sensing currents ranging from 5 mA to 1000 mA. The proper selection of sensing current can be justified by the linearity between Vsd and temperature, which is further assessed by Pearson correlation coefficient ρlinear with 1 indicating perfect linearity

    E 2

    where cov denotes the covariance, and σ is the standard deviation. The left part of Table I lists that a sensing current of Isense = 100 mA gives the best linearity, whereas smaller and larger sensing currents result in a slightly worse performance.


    2) Sensitivity: A viable TSEP sampling hardware requires a sensitivity SVT above 1 mV/K, which is defined as

    E 3

    Given a constant sensing current density, the temperature derivative of (1) yields

    E 4

    It indicates that when Vpn dominates the device’s voltage drop, the sensitivity decreases with the sensing current due to its negative logarithmic dependency in (4) and is also validated in the left part of Table I. All scenarios listed in the table meet the 1 mV/K requirement. Note that a higher or a lower SVT can also be selected according to the specific acquisition system.

    TABLE I--CALIBRATION RESULTS UNDER DIFFERENT SENSING CURRENTS AND GATE TURN-OFF VOLTAGES.-

    3) Self Dissipation: To ensure accurate junction temperature measurement in the cooling phase, the self heating effect of the sensing current shall be negligible. A self-dissipation ratio is defined as

    E 5

    where Psense is the power dissipated by the sensing current which is generated by the measured TSEP voltage Vsd@Isense under Isense. Prate is the rated power dissipation of the tested device provided in datasheet. Generally, Prate can cause more than 100 C junction temperature increase. ηsd ≤ 1% implies that the temperature increase by the sensing current is less than 1 C (regarded as negligible here). Table I shows, except the cases of 500 mA and 1000 mA, all other scenarios meet the requirement of ηsd ≤ 1%.

    B. Impact of Sensing Current Density on Dynamic Performance

    During the period from 1 to 2 in Fig. 1, electrical and thermal transients occur simultaneously. This coupling poses challenge to extract the correct cooling curve of power devices. To address this issue, the standard JESD 51-1 introduces a delay time (tMD) to remove unwanted electrical transients plus a linear extrapolation to estimate the temperature at t = 0 s.

    However, SiC MOSFETs are likely to suffer from long tMD, e.g., more than 600 µs under Isense = 5 mA in Fig. 3(b). It is much longer than the time scale of the chip’s thermal transient and hinders getting an accurate thermal structure property. However, by increasing Isense to 100 mA, tMD reduces to an acceptable 42 µs. Further increasing the sensing current has a limited effect on reducing tMD but rapidly increases the self-dissipation ratio.

    Taking both static and dynamic performances into account, a sensing current of 100 mA achieves better overall performance for this study case.

    IV. Calibration: Impact of Gate Voltage

    A. Gate Turn-Off Voltage Selection

    TCAD simulation in Fig. 4 shows that the electronic density changes dramatically in the channel region when the gate voltage varies from 0 V to -4 V but remains steady for a gate voltage less than -6 V to fully turn the channel off. This behavior is fundamentally different from Si devices, where a gate voltage of 0 V is sufficient as shown in Fig. 5(a).

    Fig.-4.-The-electronic-density-distribution-of-the-SiC-MOSFET-under-different-Vgsoff-in-TCAD-simulation
    Fig. 5. Static and dynamic impacts of the gate voltages on SiC MOSFET

    Although existing studies have experimentally shown that Vgsoff = −6 V is enough to turn off the channel of SiC MOSFETs, it may not be applicable to all SiC MOSFETs due to different die designs and manufacturing processes. Different devices will be discussed in Section VI-C and the following part will focus on two methods for gate turn-off voltage selection.

    1) Method 1 – Output Characteristic under Sensing Current: Output characteristic curves of body diode under the sensing current range can shift significantly from each other in case of insufficient gate voltages, such as Vgs = −3 V in Fig. 5(b) but start to overlap as the gate voltage approaches -6 V. To quantify this effects, an electrical conductance gdiode at the sensing current is defined as

    E 6-7

    When the entire current flows through the internal body diode, the conductance is independent of gate voltage and becomes a constant. The minimum Vgs ensuring a completely-off channel can then be identified by (7), for example, Vgs = −4.5 V for this case study as shown in Fig. 5(c).

    2) Method 2 – Calibration Curves with Varied Gate Voltages: The calibration curves show the relationship between the sensing current and TSEP, and shall overlap with each other under various gate voltage provided a fully turned-off MOSFET channel. At the meantime, TSEP is linearly dependent on temperature. Therefore, similar to method 1, the criteria defined in (8) can be introduced to identify the minimum reasonable gate tun off voltage, which is a slightly different Vgs < −5 V than Vgs < −4.5 V as shown in Fig. 5(d).

    E 8
    B. Static and Dynamic Impacts of Gate Voltages

    The calibration results under various gate voltage are also evaluated with respect to the linearity, sensitivity, and self-dissipation ratio. The measured results and its analytical summary are show in Fig. 5(d) and the right-hand side of Table I. When the gate voltage changes from 0 V to -3 V, the linearity deteriorates significantly compared to the other gate voltages. This poor linearity indicates that the measured Vsd is not primarily determined by the pn junction.

    Moreover, by adjusting the gate turn-off voltage from 0 V to -8 V, the sensitivity and the self-dissipation ratio changes minorly. Regarding the dynamic behavior, the time delays under varied turn-on and turn-off gate voltages are investigated in Figs. 5(f) and (g), respectively. The effect of the gate voltage on the measurement delay time is almost negligible. Within the device’s maximum allowable gate voltage range, a lower gate turn-off voltage can improve the static behavior without significantly affecting the dynamic performance of the thermal transient measurement.

    V. Cooling Curve Measurement

    Once the calibration is completed, the established relationship between Vsd and temperature can be utilized for cooling curve measurements, where the selection and impacts of heating current, gate turn-on voltage etc. will be evaluated.

    A. Impact of Sensing Current

    Fig. 6(a) shows the cooling curves of a SiC MOSFET under same test conditions except the sensing current. Ideally, the two measurements shall overlap completely. However, the case with Isense = 5 mA takes 663 µs to reach the state 2 , comparing to only 42 µs under Isense = 100 mA. This is due to the fact that the body diode requires sufficient minority carrier charge accumulation to turn on, and it takes longer for a smaller sensing current.

    Fig. 6. Cooling curve measurement under varied conditions

    The above measurements validate the dynamic study in Section III-B. Furthermore, the frequency analysis in Fig. 6(b) shows measurements with Isense = 5 mA exhibit large high-frequency noises, while it decays rapidly when Isense = 100 mA. At a certain bandwidth ∆f of the measurement, the noise can be modeled as a Johnson-Nyquist form, that is,

    E 9

    where Rpn is the resistance of the body diode at Isense, i.e., Rpn ≈ kbT /qIsense. It indicates that the noise in the measured voltage diminishes with the square root of the sensing current. Thus, a higher sensing current is advantageous for both shorter electric transients and lower noise.

    B. Impact of Gate Turn-Off Voltage

    Fig. 6 c) illustrates a series of cooling curves measured under various gate voltages. (Note that each cooling measurement shares the same gate voltage with its used calibration curve, which can be found in Table I). Abnormal temperature rises at approximately 2×10−4 s can be observed with severely insufficient gate voltages (e.g., 0 V and -1 V) but disappears with gate voltages less than -3 V.

    This phenomenon is inconsistent with physical principles as the cooling stage does not involve any heat injection and therefore junction temperature rise shall not appear. Similar behavior is also observed with a conclusion of imperfect SiC MOSFET structure. Another reason for this inconsistency can be the insufficient gate turn-off voltage based on above findings. Moreover, temperature measurements go below the ambient temperature of 25 C for voltages less than -3 V but turn normal by further lowering voltage to -6 V and beyond.

    Similar effects can be observed in Fig. 6(d) where the thermal impedance curves, reflecting the thermal structure of a semiconductor package, remains unchanged until the sufficient enough gate voltage is applied. These inconsistencies underscore the significance of the gate turn-off voltage.

    C. Impact of Gate Turn-On Voltage and Heating Current

    Gate turn-on voltage decides the channel voltage drop in the heating stage. Together with the heating current, a higher power dissipation results in a higher junction temperature. A maximum temperature difference of up to 20 C and 80 C are observed in Fig. 6(e) and (g) for different Vgson and Iheat. The derived thermal impedance curves, however, barely change as shown in Fig. 6(f) and (h). Additionally, the measurement delay time remains unchanged. Thus, conclusion can be made that Vgson and Iheat have negligible affect on the thermal characterization given a sufficient gate turn-off voltage and sensing current.


    VI. A Guideline for Reproducible Transient Thermal Measurements of SiC MOSFETs


    A. Junction-to-Case Thermal Impedance Measurement

    Cooling curve measurement evaluates the thermal impedance from the device junction temperature to the ambient. More importantly, it can be used to identify the junction-to-case thermal impedance, which attracts more industrial interest. The JESD 51-14 standard clearly states the procedure by using transient dual interface approach. The overall principle is to conduct two transient thermal measurements of the identical device but with and without thermal interface material (denoted as tim and dry, respectively).

    The two derived thermal curves start to separate as soon as the heat flow enters the TIM layer due to the surface roughness between package and cold-plate. Same procedure is followed in this paper based on the testing platform in Fig. 7(a) and previously identified test conditions of Vgs_off = -6 V and Isense = 100 mA. Subsequently, the cooling curves and thermal impedance curves are obtained as shown in Fig. 7(b) and (c). A clear separation point, or namely junction-to-case thermal impedance, can be observed at 0.8 K/W in Fig. 7(c) and in the thermal structure function curve in Fig. 7(d).

    Fig. 7. Experimental measurement of junction-to-case thermal impedance of the SiC MOSFET
    B. Transient Thermal Measurement Guideline

    Based on the analysis and results discussed earlier, a flowchart to achieve a reproducible transient thermal measurement is provided in Fig. 8. It is evident that the gate turn-off voltage (Vgsoff) is a critical parameter that needs to be determined initially. Method 1 or 2 from Section IV-A can be applied. Certain margin can be added within the maximum gate voltage too as it benefits both static and dynamic states.

    Subsequently, the sensing current (Isense) should be carefully selected. Too large or small sensing currents may not be conducive to accurate transient thermal measurements. It is important to ensure that the pn-junction dominates the measured drain-source voltage (Vsd) in terms of linearity, sensitivity, self-dissipation ratio, and measurement delay. Both the static and dynamic states should be evaluated comprehensively.

    Fig. 8. A flowchart for reproducible transient thermal measurement.

    Once Vgsoff and Isense have been determined, the cooling curve measurement can be conducted accordingly. A final validation process can be added by varying the heating current (Iheat) or gate turn-on voltage (Vgsoff) to further validate the accuracy and reproducibility of the measurements.

    C. Viability Validation

    To validate the viability of the proposed flow, three additional devices from different vendors are tested with key information listed in Table II. Device 1 has been investigated in Section IV-V in detail. Fig. 9 shows the results of determining Vgsoff based on method 2. It is apparent that Vgsoff = −6 V, employed by multiple existing studies, is not sufficient enough for device 3 and 4 that require -10 V and -13 V to turn their channel off completely.

    Fig. 9. Selection of Vgsoff and Isense for additional three different devices listed in Table II

    But it should be noted that these two values exceed the maximum allowable gate voltages according to devices data sheet. It implies that the current thermal transient measurement method based on Vsd may not be applicable to device 3 and 4 without exceeding the maximum gate turn-off voltage. Moreover, the selection of Isense with respect to the dynamic performance can be found in Fig. 9 together with the corresponding static performances listed in Table II. 100 mA is a proper sensing current for all 4 devices due to the short tMD and negligible self dissipation. It should be noted that the sensing current is around 5.26 ‰ of the rated current of the SiC MOSFET, which is different from Si devices.

    TABLE II--COMPARISON OF DIFFERENT DEVICES

    VII. Conclusion

    This paper investigates the thermal characterization of SiC MOSFET based on the body diode source-drain voltage. Two key steps, namely the calibration and cooling curve measurement, are evaluated comprehensively. The selection of key testing conditions, i.e., sensing/heating currents, gate turn-off/turn-on voltages, are thoroughly assessed based on their impacts on the thermal characterization and the following conclusions are achieved:

    1. Low enough gate turn-off voltage shall be used in both calibration and cooling curve measurement to ensure a completely shut channel and correct thermal impedance measurement. However, the required negative gate voltage may exceed the maximum allowable range, which causes the current thermal transient measurement method based on Vsd being not available for these devices within the maximum allowable gate voltage.
    2. Insufficient sensing current deteriorates the dynamics in terms of longer electrical disturbance and more noises, while too large sensing current sacrifices the steady-state performance in particular of a large self dissipation ratio.
    3. Gate turn-on voltage and heating current have negligible impacts on the measured thermal impedance. The consistency of the thermal impedance under varied gate turn-on voltage or heating current can be used as a validation.

    Besides, a guide flowchart to perform reproducible transient thermal measurement for SiC MOSFETs is provided in this paper, which includes the selection of the electrical parameters and a validation process.

    Authors

    Yi Zhang, Yichi Zhang, Zhiliang Xu, Zhongxu Wang, Voon Hon Wong, Zhebie Lu, Antonio Caruso

    Original – Research Gate

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  • Vishay Intertechnology Introduced a New 30 V N-Channel TrenchFET Gen V Power MOSFET

    Vishay Intertechnology Introduced a New 30 V N-Channel TrenchFET Gen V Power MOSFET

    2 Min Read

    Vishay Intertechnology, Inc. introduced a versatile new 30 V n-channel TrenchFET® Gen V power MOSFET that delivers increased power density and enhanced thermal performance for industrial, computer, consumer, and telecom applications.

    Featuring source flip technology in the 3.3 mm by 3.3 mm PowerPAK® 1212-F package, the Vishay Siliconix SiSD5300DN provides best in class on-resistance of 0.71 mΩ at 10 V and on-resistance times gate charge — a critical figure of merit (FOM) for MOSFETs used in switching applications — of 42 mΩ*nC.

    Occupying the same footprint as the PowerPAK 1212-8S, the device released today offers 18 % lower on-resistance to increase power density, while its source flip technology reduces thermal resistance by 63 °C/W to 56 °C/W. In addition, the SiSD5300DN’s FOM represents a 35 % improvement over previous-generation devices, which translates into reduced conduction and switching losses to save energy in power conversion applications.

    PowerPAK1212-F source flip technology reverses the usual proportions of the ground and source pads, extending the area of the ground pad to provide a more efficient thermal dissipation path and thus promoting cooler operation. At the same time, the PowerPAK 1212-F minimizes the extent of the switching area, which helps to reduce the impact of trace noise.

    In the PowerPAK 1212-F package specifically, the source pad dimension increases by a factor of 10, from 0.36 mm2 to 4.13 mm2, enabling a commensurate improvement in thermal performance.  The PowerPAK1212-F’s center gate design also simplifies parallelization of multiple devices on a single-layer PCB.

    The source flip PowerPAK1212-F package of the SiSD5300DN is especially suitable for applications such as secondary rectification, active clamp battery management systems (BMS), buck and BLDC converters, OR-ing FETs, motor drives, and load switches. Typical end products include welding equipment and power tools; servers, edge devices, supercomputers, and tablets; lawnmowers and cleaning robots; and radio base stations.

    Original – Vishay Intertechnology

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  • MCC Semi Unveils a New 1700V SiC MOSFET

    MCC Semi Unveils a New 1700V SiC MOSFET

    1 Min Read

    Micro Commercial Components unveiled 1700V SiC MOSFET – SICW400N170A-BP. Designed to elevate power conversion in a range of applications, this MOSFET features ultra-low on-resistance of only 400mΩ and high blocking voltage capability. SICW400N170A-BP SiC MOSFET enables high-speed switching while ensuring minimal conduction losses — essential requirements for optimizing frequency-dependent systems. 

    A standard, yet durable TO-247AB package delivers effective operation at a gate-source voltage of 20V with superior thermal stability and an operating junction temperature of +175°C. 

    This unwavering reliability in harsh conditions only adds to the component’s appeal and versatility for various high-voltage applications, including EV charging stations and renewable energy systems.

    Features & Benefits:
    • High blocking voltage capability (1700V)
    • Ultra-low on-resistance (400mΩ) enhances efficiency
    • Low capacitance enables faster switching
    • Excellent thermal stability
    • High operating junction temperature (to +175°C)
    • Standard TO-247AB package

    Original – Micro Commercial Components

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  • MCC Introduced a New 1200V SiC MOSFET

    MCC Introduced a New 1200V SiC MOSFET

    1 Min Read

    Micro Commercial Components introduced its latest high-performance component — 1200V SiC N-channel MOSFET. With an impressively low on-resistance of just 28mΩ at a gate-source voltage of 18V, SICW028N120A4-BP is engineered to deliver in demanding high-power applications. 

    Housed in a TO-247-4 package, this MOSFET works well with the popular D2PAK 4-pin footprint and includes a Kelvin source pin for significant reduction in switching losses and a boost in energy efficiency. 

    A high operating junction temperature of up to +175°C and excellent thermal stability ensure this new SiC MOSFET will revolutionize power management in a diverse range of industrial and commercial devices that must perform in harsh conditions.

    Features & Benefits:

    • 1200V blocking voltage capability
    • 28mΩ low on-resistance
    • Kelvin source pin for enhanced switching
    • Avalanche ruggedness for durability
    • Excellent thermal stability
    • High operating junction temperature range (+175°C)
    • D2PAK-compatible 4-pin TO-247-4 package

    Original – Micro Commercial Components

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  • PANJIT Introduced New P-Channel and N-Channel MOSFETs to Boost Automotive Electronic Systems

    PANJIT Introduced New P-Channel and N-Channel MOSFETs to Boost Automotive Electronic Systems

    2 Min Read

    PANJIT introduced new P-channel and N-channel MOSFETs designed to boost automotive electronic systems. The P-channel MOSFETs, with AEC-Q101 qualification and a high 175°C junction temperature, offer optimal choices for design engineers seeking reliability and simplified circuitry. These MOSFETs, minimizing RDS(ON) and maximizing avalanche ruggedness, are available in flexible packages (DFN3333-8L, DFN5060-8L, DFN5060B-8L, TO-252AA, TO-263, and TO-263-7L).

    PANJIT’s N-channel power MOSFETs employ advanced trench technology, delivering excellent figure of merit (FOM), lower RDS(ON), and capacitance. Available in low-profile packages (DFN3333-8L, DFN5060-8L, DFN5060B-8L, TO-252AA), these MOSFETs contribute to efficient and reliable PCB layouts.
    By combining innovation with reliability, PANJIT’s low voltage MOSFETs simplify power design circuitry, addressing the evolving needs of automotive design engineers.

    These components are a testament to PANJIT’s commitment to shaping the future of automotive electronics, offering optimal solutions for high-performance automotive applications.

    Key Features of 30V & 40V Automotive-Grade P-Channel MOSFET:

    • P-channel enhancement mode logic level MOSFETs
    • Low RDS(ON) to minimize conduction losses
    • Package with low thermal resistance
    • 100% unclamped inductive switching (UIS) tested
    • Electrostatic sensitive device (ESD) capable
    • AEC-Q101 qualified and PPAP capable
    • 175°C operating junction temperature
    • Available in TO-263-7L Package

    Key Features of 30V & 40V Automotive-Grade N-Channel MOSFET:

    • 30V & 40V N-channel advanced trench
    • Low RDS(ON) to minimize conduction losses
    • Low FOM to minimize driver losses
    • Standard and logic level available
    • AEC-Q101 qualified and PPAP capable
    • 175°C operating junction temperature

    Original – PANJIT International

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