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Navitas Semiconductor announced its participation in the upcoming Power Electronics International conference on April 16th– 17th 2024, in Brussels, Belgium.
Grid reliability is a key factor in a $1.3 trillion power semiconductor opportunity as Navitas’ technologies accelerate the transition from fossil fuels to renewable energies. Navitas will introduce the latest GaNFast™ and GeneSiC™ products to the European audience, including new Gen-3 Fast SiC for high-power and higher-speed performance, plus GaNSafe™ – the world’s most protected GaN power devices.
Navitas will present the following on April 17th:
- “3.3 kV SiC MOSFETs Accelerate Grid-Connected Energy Storage,” Dr. Ranbir Singh, EVP GeneSiC
Synopsis: The grid supplies energy from generators and delivers it to customers via transmission and distribution (T&D) networks. In the U.S., the use of electricity storage to support and optimize T&D has been limited due to high storage costs and limited design and operational experience. Recent improvements in storage and power technologies, however, coupled with changes in the marketplace, herald an era of expanding opportunity for electricity storage. SiC inverters will revolutionize electricity delivery, renewable energy integration, and energy storage. It is well-recognized that silicon-based semiconductors have inherent limitations that reduce their suitability for utility-scale applications.
- “Bi-directional circuits open up new opportunities in off-grid applications,” Alfred Hesener, Senior Director Industrial and Consumer Applications
Synopsis: Bi-directional circuits are critical to effectively smooth the supply/demand variation in renewable energy applications. In the past, they were expensive to make and complex to implement in power electronics applications. Wide bandgap GaN power ICs with integrated drive and advanced circuit functions deliver easy-to-use, reliable, high power density, and functionality for power factor correction circuits, solar inverters, and solid-state circuit breakers.
Original – Navitas Semiconductor
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Wolfspeed, Inc. hosted Senator Thom Tillis (R-NC) and other local officials, community partners, and employees at a ceremony to celebrate the topping out of construction at the $5 billion John Palmour Manufacturing Center for Silicon Carbide. Located in Chatham County, North Carolina, the JP will produce 200mm silicon carbide wafers, significantly expanding Wolfspeed’s materials capacity, and meet the demand for next generation semiconductors critical to the energy transition and AI.
“We are excited to mark this critical milestone alongside our hard-working team, loyal customers, community partners, and ardent supporters like Senator Thom Tillis,” said Wolfspeed President and CEO, Gregg Lowe.
“This facility is a testament to Wolfspeed’s commitment to our local community and domestic workforce, furthering our position as the global leader in silicon carbide production. The JP will help maintain America’s lead in energy innovation, and unlock significant benefits for our local community by growing the state’s economy by more than $17.5 billion over the next two decades and creating 1,800 good-paying jobs by 2030.”
“Wolfspeed’s $5 billion investment in Chatham County is another example of why North Carolina is the best state in the country to do business,” said Senator Tillis. “I was proud to vote in favor of the CHIPS and Science Act, which provides critical support for domestic semiconductor manufacturing, and I applaud Wolfspeed’s commitment to developing technology here in North Carolina that supports our national security and economic interests.”
The JP represents a total investment of $5 billion, complemented by public and private support, to help accelerate the transition from silicon to silicon carbide and ramp up supply of this material recently deemed as critical to the energy transition by the U.S. Department of Energy. By the end of 2024, phase one of construction is expected to be completed on the 445-acre site.
The ramp of the JP will support recently signed customer agreements with Renesas, Infineon, and additional companies, while driving meaningful progress towards Wolfspeed’s long-term growth strategy. The JP will primarily produce 200mm silicon carbide wafers, which are 1.7x larger than 150mm wafers, translating to more efficient wafers and ultimately, lower costs. The JP underpins Wolfspeed’s vision of accelerating the adoption of silicon carbide semiconductors across a wide array of end-markets and unlocking a new era of energy efficiency.
Wolfspeed currently produces more than 60% of the world’s silicon carbide materials at its Durham, N.C. headquarters, and is engaged in a $6.5 billion capacity expansion effort to dramatically increase production.
Original – Wolfspeed
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Abstract
In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics.
The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (Vcut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Qgd). Through TCAD simulation, the HJD-ATMOS decreases Vcut-in by 53.04% compared to the C-ATMOS. Both Qgd and switching loss are reduced, with a decrease of 31.91% in Qgd and 40.29% in switching loss.
1. Introduction
The wide bandgap semiconductor properties of silicon carbide (SiC) make it a promising candidate for the development of future power switching devices. This is primarily due to SiC possessing properties such as a strong breakdown field, high physical and chemical stability, high thermal conductivity, and high electron saturation velocity.
SiC devices can operate in harsh environments due to their wide band gap of 3.25 eV and high thermal conductivity of 5 W/(cm·K). The SiC MOSFET is the most significant SiC power switching device due to its lack of trail current. This reduces switching loss and radiator volume, improving system power density.
SiC MOSFETs commonly make use of parasitic body-PN diodes as freewheeling diodes (FWD) in power inverter and converter systems. However, parasitic body-PN diodes in SiC MOSFETs are not ideal for use as freewheeling diodes. The reasons for this are as follows: Stacking faults (SFs) in SiC devices may cause reliability issues and increase conduction loss.
Although recent papers concerning the measured degradation of SiC MOSFETs show a high level of current threshold (about 5× the nominal current or more than 1000 A/cm2) for the starting of bipolar degradation, bipolar degradation effects can still occur in SiC MOSFETs under large cyclic pulse current densities. This will limit the application of SiC MOSFET devices in key areas, such as the surge current that flows through a diode during the start-up of a power converter, which can be more than ten times its rated current.
Furthermore, the body diode’s Vcut-in voltage (~2.7 V) is much higher than that of its silicon counterparts due to SiC’s wide bandgap. To overcome the drawbacks of parasitic body-PN diodes, numerous approaches have been devised to deactivate them. One approach is to integrate SiC MOSFETs with Schottky barrier diodes (SBDs). However, the use of external diodes not only introduces parasitic inductance, limiting switching frequency, but also consumes additional area in the package. And Schottky contacts suffer from a significant increase in reverse leakage current at high temperatures.
Furthermore, SiC MOSFETs with low-barrier and heterojunction diodes are available. Heterojunction diodes formed between polysilicon and SiC are attractive. Shenoy and Baliga, and Yamagami et al. presented studies on heterojunction diodes using P-Poly-Si and n-6H-SiC, and Poly-Si and 4H-SiC, respectively.
Both studies demonstrated low-forward-voltage Schottky-like characteristics. Ni et al. proposed a trench SiC MOSFET integrating polysilicon/SiC HJD, exhibiting excellent freewheeling diode (FWD) performance in both the first and third quadrants. The HJD’s unipolar behavior, similar to that of a Schottky diode, effectively suppresses the turn-on of the problematic body diode, mitigating the aging degradation observed in conventional SiC MOSFETs.
Additionally, HJDs reduce reverse recovery voltage and losses, enhancing long-term operational reliability. Furthermore, HJD integration eliminates the need for a separate SBD, leading to a smaller chip area, simpler packaging, and reduced overall system cost. This also minimizes parasitic inductance arising from additional components.
A novel asymmetric trench SiC MOSFET with a heterojunction diode at the right of the gate trench is proposed and simulated in this paper. The structure includes a trench gate with split-gate electrodes and a thicker P-Poly-Si layer, resulting in reduced gate charge and improved switching performance. To suppress the depletion layer, an n-type doped current spreading layer (N-CSL) is formed under the entire P-well region.
To maintain the breakdown voltage (BV) of the device structure while maintaining transfer and output characteristics similar to those of C-ATMOS, the depth of the P-well on the right side is not changed. The N-channel (Nch) is positioned below the P-Poly-Si and in contact with the CSL. The integrated HJD structure of the proposed device eliminates the requirement for an anti-parallel SiC SBD during reverse conduction. The HJD turns on at a low source–drain voltage (Vsd), thus eliminating bipolar degradation by inactivating the body diode. The split gate results in a decrease in gate charge, leading to a reduction in switching losses in the HJD-ATMOS without affecting other characteristics.
2. Device Structure and Mechanism
The schematic cross section of HJD-ATMOS and C-ATMOS is shown in Figure 1. Similar to C-ATMOS, the device forms an inversion layer channel in the first quadrant to facilitate electron conduction. The N-CSL layer on the N-drift region reduces the on-resistance. Deep P-wells are used to reduce the electric field stress in the gate oxide at the trench bottom and corner.
The primary distinction is the body diode structure. The Nch region under the P-Poly-Si provides a low-barrier path for electrons. Meanwhile, the HJD-ATMOS has a split gate and HJD structure on the right of the gate oxide layer. The split gate structure uses only a portion of the trench space for the gate electrode, while the other part is thicker P-Poly-Si that forms a portion of the HJD structure. The HJD-TMOS facilitates low-voltage conduction by allowing electrons to cross the lower heterojunction barrier in the third quadrant. The structure of Nch and N-channel doping concentration (Nnch) will be further discussed based on this optimization in this paper. Device specifications are presented in Table 1.
Figure 1. Schematic cross section of (a) HJD-ATMOS and (b) C-ATMOS.
Table 1. Main parameters used in the simulation.
Sentaurus TCAD simulations are used to analyze the performances of the HJD-ATMOS and the C-ATMOS, considering doping and temperature-dependent Shockley–Read–Hall and Auger recombination, doping-dependent transport, impact ionization, band narrowing, high-field velocity saturation, and mobility degradation, as well as fixed charges at the SiC/SiO2 interface for closer simulation results to experimental data.
The energy band diagram of the P-Poly-Si/N-SiC heterojunction at thermal equilibrium is shown in Figure 2b. The energy band diagram at thermal equilibrium along the A-A’ cut-line is shown in Figure 2a. The heterojunction has a conduction energy gap of 0.46 eV and a valence barrier energy gap of 1.78 eV. The electron barrier height ΦBN is determined by the Fermi level energy Ef and the conduction band peak energy Ec, which is about 1.39 eV.
Figure 2c shows the simulated carrier density at the heterojunction interface under forward bias at the rated voltage. Electrons are injected from N-SiC to P-poly, but there are few holes from P-poly to N-SiC due to the high hole barrier. Therefore, the HJD exhibits unipolar action, similar to the SBD.
Figure 2. (a) Schematic cross section of HJD-ATMOS; (b) energy band diagram at thermal equilibrium along the A-A’ cut-line; (c) carrier density of the HJD when forward biased at rated voltage.
We also constructed a 3D band diagram of the device to better observe the working state of the device. Figure 3a shows the 3-D conduction band energy distribution of the device at Vds = 10 V and Vgs = 15 V. The band energy of Nch is higher than that of N-CSL, which prevents electron current from flowing to P-poly and enables the device to work normally like C-ATMOS.
Figure 3b shows the distribution of the devices when Vds = −5 V and Vgs = −5 V. The band energy of Nch is lower than that of N-CSL, resulting in electron current flowing from N-CSL to P-poly and preventing the turn-on of parasitic body-PN diodes.
Figure 3. Three-dimensional conduction band energy distribution between P-poly, gate, Nch, N-CSL, and P-well (a) when conduction is forward and (b) when conduction is reverse.
Figure 4 shows the distribution of the total current density, hole current density, and electron current density of the device. From the total current density distribution, it can be seen that the current does not flow from P-Poly-Si to P-well. But a high current density is also noted at the gate corner of P-Poly-Si, which should be noted in use. From the hole current density distribution, it can be seen that holes do not enter N-drift.
This is due to the difference in the band gap between SiC and polysilicon. Since the energy barrier height between the SiC and polysilicon junctions in the valence band is very large, in the HJD-ATMOS, electron current can move toward the source while hole current cannot move toward the drain. The device can operate normally at electron current densities of 10 A/cm2 and 500 A/cm2.
Figure 4. (a) Total current density distribution, (b) hole current density distribution, and (c) electron current density distribution at low and high current in the reverse conduction.
Figure 5 shows the I–V curves of HJD-ATMOS and C-ATMOS in forward and reverse conduction at room temperature. The steeper slope of the I–V curve of HJD-ATMOS in the first quadrant indicates that its specific on-resistance (Ron,sp) is lower than that of C-ATMOS. This is because the presence of Nch in HJD-ATMOS results in a smaller depletion region of P-well on N-CSL, leading to a wider current conduction region.
According to the calculations, at Vgs = 15 V and Ids = 200 A/cm2, the Ron,sp values for HJD-ATMOS and C-ATMOS are 1.35 mΩ∙cm2 and 1.46 mΩ∙cm2, respectively. In the third quadrant, at Ids= −10 A/cm2, HJD-TMOS exhibits a significantly lower Vcut-in of only 1.39 V compared to the PN diode of C-TMOS. As a result, HJD-ATMOS is capable of reducing switching losses.
The rated operating current of the device in the third quadrant is generally Ids = −200 A/cm2. This means that the proposed HJD-ATMOS has a clear advantage over C-ATMOS in that it can start working at a lower voltage. The hole density distribution diagram in Figure 5 for Ids = −200 A/cm2 shows that the integrated HJD effectively suppresses minority carrier injection, reducing bipolar degradation.
Figure 5. First and third quadrant characteristics of HJD-ATMOS and C-ATMOS.
In Figure 6, the local magnification shows that the HJD-ATMOS is affected by current spikes due to leakage. The figure demonstrates the change in breakdown voltage as a function of h and w when Nnch is, respectively, 2 × 1017 cm−3 and 2.5 × 1017 cm−3. It can be observed that when Nnch is 2.5 × 1017 cm−3, with h at 0.25 μm and w at 0.5 μm, the spike in the current is large, indicating the occurrence of leakage. When Nnch is 2.5 × 1017 cm−3, increasing h to 0.30 μm and w to 0.4 μm also results in leakage.
However, when Nnch is 2.0 × 1017 cm−3 and h increases to 0.3 μm, the device does not exhibit leakage, demonstrating that variations in Nnch have a significant impact on device performance. As shown in Figure 7, Vcut-in varies significantly with h. The minimum point of Vcut-in is 1.31 V at Nnch = 2 × 1017 cm−3, which is lower compared to its value of 1.71 V at Nnch = 2.5 × 1017 cm−3 and h = 0.2 μm.
This point represents the critical condition for the device not exhibiting leakage when Nnch = 2.5 × 1017 cm−3. After h is greater than 0.25 μm, the variation in Vcut-in with h tends to be flat, and if the value of h is larger, the protective effect of P-well on the gate oxide will also be weakened, and it will also increase the difficulty of process manufacturing.
As can be seen from Figure 8, when the device Vds is 0 V, Nnch is 2.5 × 1017 cm−3, and h is 0.25 μm, the HJD-ATMOS has more leakage than the device with Nnch is 2.0 × 1017 cm−3 and h is 0.30 μm. The darker regions in the current density plot for the HJD-ATMOS with Nnch at 2.5 × 1017 cm−3 and h at 0.25 μm are larger than those with Nnch at 2.0 × 1017 cm−3 and h at 0.30 μm, indicating higher leakage currents. This also confirms the hypothesis that the breakdown voltage spike is caused by heterojunction leakage. So the results indicate that Nnch = 2 × 1017 cm−3, h = 0.3 μm, and w = 0.5 μm are the optimal values.
Figure 6. The breakdown voltage varies with h, w, and Nnch, when Nnch is 2.0 × 1017 cm−3 and 2.5 × 1017 cm−3, h is 0.20 μm, 0.25 μm and 0.30 μm, and w is 0.1 μm to 0.5 μm, respectively.
Figure 7. Vcut-in varies with h, w, and Nnch, when Nnch is (a) 2.0 × 1017 cm−3, and (b) 2.5 × 1017 cm−3.
Figure 8. Current density distribution when (a) Nnch is 2.5 × 1017 cm−3, h is 0.25 μm, and (b) Nnch is 2.0 × 1017 cm−3, h is 0.30 μm at Vds = 0 V.
3. Simulation Results and Discussion
Figure 9 shows the capacitances of HJD-ATMOS and C-ATMOS. Gate voltage was fixed at 0 V, a 1 MHz AC signal was applied, and drain voltage was swept from 0 to 1000 V. HJD-ATMOS has lower gate-to-source capacitance (Cgs) than C-ATMOS due to the smaller contact area with the source caused by the split gate structure. HJD-ATMOS’s gate-to-drain capacitance (Cgd) does not decrease.
This is because the P-well blocks the right side of the gate of C-ATMOS, performing a similar function as the split gate. Therefore, it can be observed that the Ciss (Cgs + Cgd) of the HJD-ATMOS with split gates is also smaller than that of the C-ATMOS.
Figure 9. The device capacitance of HJD-ATMOS and C-ATMOS.
Gate-to-drain charge (Qgd) is critical for power device switching speed in device applications. Figure 10 shows a test circuit to simulate HJD-ATMOS and C-ATMOS gate charges during turn-on. The miller plateau height of HJD-ATMOS is less than that of C-ATMOS, indicating that the threshold voltage of HJD-ATMOS is smaller than that of C-ATMOS.
Because the gate charge is proportional to the gate capacitance, the HJD-ATMOS has a lower gate charge (Qg) and Qgd compared with the C-ATMOS. The Miller platform in HJD-ATMOS is shorter because of the reduced gate area. The Qgd values for HJD-ATMOS and C-ATMOS are 32 nC/cm2 and 47 nC/cm2, respectively. Qgd of HJD-ATMOS decreased by 31.91% compared to C-ATMOS. Reduced Qgd leads to a smaller high-frequency figure of merit in HJD-ATMOS.
Figure 10. The gate charge characteristics of HJD-ATMOS and C-ATMOS.
Figure 11 shows the electric field distribution at the breakdown of HJD-ATMOS and C-ATMOS. The electric field at the gate oxide of HJD-ATMOS is smaller than that of C-ATMOS. This is because the presence of the Nch introduces a portion of the electric field into this region, which alleviates the electric field that the gate oxide withstands.
Although increasing the electric field at the heterojunction raises leakage current risk, it is a trade-off for improved reverse conduction performance. Figure 12 shows the blocking characteristics of the HJD-ATMOS and the C-ATMOS at room temperature and high temperature. At room temperature, the data are represented by solid lines, whereas at elevated temperatures, they are depicted by dashed lines. HJD-ATMOS and C-ATMOS have similar breakdown voltages at room temperature. But the leakage current of the HJD-ATMOS increases at high temperature due to the increased thermal energy of the charge carriers.
The generation of leakage currents, as demonstrated and discussed in Figure 6 and Figure 8, arises due to leakage occurring at the heterojunction, where higher Nnch and greater values of thickness h both contribute to this effect. By improving the semiconductor material growth process, reducing defects and traps, and enhancing the material quality and interface integrity, it is possible to mitigate non-ideal scattering and trap effects experienced by charge carriers at the heterojunction interface, thus suppressing the leakage current.
While the HJD-ATMOS structure does indeed experience leakage under temperature influence, this leakage is within acceptable limits, with the level of leakage current being 1 × 10−5 μA/cm2.
Figure 11. Electric field distribution for the HJD-ATMOS and the C-ATMOS at BV.
Figure 12. Blocking characteristics of the HJD-ATMOS and the C-ATMOS.
Figure 13 shows a double pulse test circuit for investigating switching characteristics. This is a common circuit configuration employed in device testing. Stray inductance is 10 nH, and load inductance is 80 μH. The gate voltage source (Vg) is turned on from −5 V to 15 V at t = 16 µs and turned off from 15 V to 0 V at t = 11 µs.
Figure 14 shows the switching waveforms of devices. The switching speed of the HJD-ATMOS is faster than that of the C-ATMOS with an external SBD diode, which results in a smaller switching loss. Figure 15 compares the switching losses between the two devices. In HJD-ATMOS, the turn-on loss (Eon) is 0.26 mJ/cm2, and the turn-off loss (Eoff) is 0.41 mJ/cm2, which demonstrate a reduction of 62.32% and 4.65%, respectively, compared to C-ATMOS.
The total switch loss of HJD-ATMOS is reduced by 40.29% compared to C-ATMOS. This is due to the smaller Qgd compared with the C-ATMOS. Reduced switching losses in power electronic devices are instrumental in improving operational longevity and reliability. As losses during switching are directly proportional to heat generation, a significant decrease in these losses curtails thermal build-up, mitigating the risk of device overheating and extending its operational life.
This reduction also sustains lower junction temperatures, crucial for preventing material degradation in high-power-density applications where maintaining low operating temperatures is vital for ensuring long-term stability and reliability. Furthermore, minimizing switching losses allows power converters and similar equipment to function efficiently at elevated frequencies without sacrificing efficiency, empowering designers to develop compact, lightweight systems while consistently meeting reliability standards.
Figure 13. A circuit for simulating switching with a double pulsed test.
Figure 14. The switching characteristics of HJD-ATMOS and C-ATMOS, including the (a) turn-on process and (b) turn-off process.
Figure 15. Switching loss comparison of IJ-ATMOS and C-ATMOS.
The majority of the process steps for HJD-ATMOS, including epitaxial growth, N+ source and P-well implantation, trench etching, P-base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition, and metallization, are fully compatible with the manufacturing processes of C-ATMOS.
The N-channel region is formed by ion implantation at the bottom of the trench after trench etching. The split gate is formed by etching after trench oxidation, resulting in a thin layer of oxide between the gate and the P-Poly-Si. The gate-P-Poly-Si trench isolation layer is formed by thermal oxidation, and the trench oxide layer is fully etched and filled with P-Poly-Si.
Table 2 compares the HJD-ATMOS and the C-ATMOS in terms of their main characteristics. Dynamic FOM indicates the value of Ron,sp × Qgd. The HJD-ATMOS performs better due to the integrated HJD structure.
Table 2. Device characteristics comparison.
4. Conclusions
This paper proposes a novel asymmetric trench SiC MOSFET with a heterojunction diode. The performance of HJD-ATMOS and C-ATMOS is compared in detail. It can be observed that HJD-ATMOS demonstrates superior third-quadrant performance with a lower Vcut-in because of the integrated HJD. Compared with C-ATMOS, the Qgd of HJD-ATMOS has decreased by 31.91%. This is because the split gate design further reduces the total gate charge, which reduces the switching loss of the HJD-ATMOS device without affecting other key characteristics.
As a result, HJD-ATMOS eliminates bipolar degradation and reduces the turn-on loss from 0.69 mJ/cm2 in C-ATMOS to 0.26 mJ/cm2. With its advantageous features, HJD-ATMOS is a strong contender for power electronic applications.
Authors
Yiren Yu, Zijun Cheng, Yi Hu, Ruiyi Lv, Shengdong Hu.
Original – MDPI
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In the paper “Milliseconds Power Cycling (PCmsec) Driving Bipolar Degradation in Silicon Carbide Power Devices”, Sibasish Laha from Fraunhofer IISB and his co-authors Jürgen Leib, Andreas Schletz, Martin Maerz, Christian Liguda, Firas Faisal and Davood Momeni describe an innovative approach to silicon carbide (SiC) power cycling.
Until now, bipolar degradation (BD) tests have not been sufficiently differentiated in the investigation of failure and fault mechanisms for SiC power devices. SiC power products may experience voltage degradation which stems from the stacking faults (SFs) growth, commonly known as BD. To properly evaluate the BD impact on the electric performance of devices, it is important to distinguish it from other stress-related degradation such as power metal or interconnection.
This aspect has not yet been addressed, although the BD mechanism is well understood. The paper outlines a methodology by modifying the power cycling test (PCsec) to PCmsec in order to systematically investigate the effect of BD while controlling the impact of thermal degradation. This method enables a thorough evaluation of the distinct influences of both degradation contributors.
The complete paper will soon be available in the CIPS proceedings. Until then, feel free to download the paper presentation on event page.
There you can also find all our contributions to CIPS 2024:- Modified Approach for the Rainflow Counting Analysis of Temperature Load Signals in Power Electronics Modules – Oral presentation by S. Letz; Co-authors: D. Zhao, J. Leib, B. Eckardt, M. März
- Milliseconds Power Cycling (PCmsec) Driving Bipolar Degradation in Silicon Carbide Power Devices – Oral presentation by S. Laha; Co-authors: D. Momeni, J. Leib, A. Schletz, M. März, C. Liguda, F. Faisal
- Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling – a Dynamic Approach – Poster by J. Breuer, F. Dresel, A. Schletz, J. Klier, J. Leib, M. März, B. Eckardt
- Wide Bandwidth PCB Rogowski Coil Current Sensor with Droop Suppression and DC Restoration for In-Situ Inverter Measurements – Poster by S. Quergfelder, J. Sax, T. Heckel, B. Eckardt, M. März
Original – Fraunhofer IISB
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Abstract
In this study, a novel integrated 4H-SiC reverse-conducting gate turn-off thyristor (GTO) featuring an N-type floating (NF) structure is proposed. The proposed NF-structured 4H-SiC GTO outperforms conventional reverse-conducting GTOs in forward conduction, effectively eliminating the snapback phenomenon.
This is achieved by increasing lateral resistance above the P-injector and modifying the electron current path during early turn-on. NF structures with a doping concentration of 2 × 1014 cm−3 and thicknesses exceeding 4 μm have been indicated to successfully eliminate the snapback phenomenon. Moreover, the anode-shorted structure enhances the GTO’s breakdown voltage and concurrently reduces turn-off losses by 85% at low current densities.
1. Introduction
In recent years, advancements in power distribution and energy transmission applications, including smart grids, ultra-high voltage power transportation, and pulse power technology, have heightened the demand for high-voltage power devices. Typically, conventional silicon (Si) power devices can withstand voltages up to 8 kV. Beyond this limit, complex arrangements of converters or devices become necessary, especially in ultra-high voltage contexts.
This necessity has shifted the focus towards wide bandgap (WBG) semiconductors, particularly 4H-SiC, renowned for their superior material characteristics. 4H-SiC is increasingly favored for fabricating ultra-high voltage and high-frequency power devices because of its exceptional properties: a bandgap three times wider than that of silicon, a critical breakdown electrical field ten times higher, and an electron saturation velocity surpassing silicon by an order of magnitude.
In recent years, significant strides have been made in refining the SiC epitaxial growth process, marked by noteworthy advancements in enhancing charge carrier lifetimes and reducing bulk- and interface-trap densities. These improvements have been instrumental in achieving substantial progress in the development of high-voltage SiC devices.
Wolfspeed (formerly known as Cree Inc., Durham, NC, USA) have announced their development of SiC MOSFETs with impressive blocking voltages of 10 kV and 15 kV. Concurrently, there has been a technological breakthrough in bipolar devices rated above 20 kV, achieving PIN diodes with blocking voltages ranging from 7 to 39 kV, further pushing the boundaries in high-voltage device engineering. In addition, 10 kV SBD and JBS diodes have also been produced.
In 2015, the voltage and current capabilities of SiC IGBTs saw a significant enhancement, reaching 27.5 kV/20 A. In 2013, Cree Inc. advanced the SiC p-GTO’s performance to 20 kV, followed by the development of a 15 kV SiC n-GTO in 2019. Furthermore, in 2017, a SiC Emitter Turn-Off Thyristor (ETO) p-ETO with a blocking voltage of 22 kV was reported, exemplifying continued advancements in SiC device technology.
Additionally, researchers are focusing on the stacking technology of SiC-based power devices for ultra-high voltage applications. In the study ‘Theoretical and Experimental Study of 22 kV SiC Emitter Turn-OFF (ETO) Thyristor’, an assessment of the forward current handling capacities of 15 kV SiC GTO (p-type), IGBT, and MOSFET at temperatures of 25 °C and 125 °C was conducted.
This analysis clearly indicates that the SiC GTO outperforms in terms of managing higher currents with the least forward voltage drop, marking it a key player for the next generation of ultra-high power devices. In the research documented in ‘Evaluation of Ultrahigh-Voltage 4H-SiC Gate Turn-OFF Thyristors and Insulated-Gate Bipolar Transistors for High-Power Applications’, simulation models were employed to validate that within a range of 20–50 kV, SiC GTOs exhibit a voltage drop of 3.4–7.8 V at a current density of 20 A/cm2 at room temperature, whereas IGBTs display a voltage drop between 4.2 and 10 V under similar conditions.
The underlying reason for this enhanced performance of SiC GTO, from the viewpoint of semiconductor current conduction, is its capability for bidirectional carrier injection and pronounced conductivity modulation in the drift region. Therefore, the SiC GTO is emerging as a highly viable option for ultra-high voltage power applications.
However, the intense conductivity modulation effect leads to an increased turn-off time, subsequently slowing down the switching speed. In the case of GTO devices, turn-off losses constitute a major part of the overall switching losses, prompting considerable efforts in recent years to minimize these losses. To enhance GTO performance, various structures such as Integrated Gate-Commuted Thyristors (IGCT), Emitter Turn-Off (ETO) Thyristors, and Reverse-Conducting GTOs (RC-GTO) have been proposed.
The Reverse-Conducting GTO (RC-GTO) introduces an innovative design that combines a diode with a GTO at the cellular level. This integrated architecture functions as a high-voltage forward switch and, when reversed, operates as a continuous current diode. Traditional GTOs, lacking reverse conduction capability, necessitate parallel connection with a reverse diode.
Thus, compared to conventional GTOs, RC-GTOs offer enhanced power density, streamlined system design, and improved thermal cycling of the chip. However, like RC-IGBTs, conventional RC-GTOs suffer from an undesirable snapback effect, which hinders the device from fully turning on. In this study, a novel integrated SiC Reverse-Conducting GTO (RC-GTO) structure featuring an N-type floating region (NF-RC-GTO) is presented. This design effectively suppresses and eliminates the snapback phenomenon, minimally impacting the primary performance. Additionally, it features low turn-off loss at low current densities.
2. Device Structure and Mechanism
Figure 1a–c illustrate the simulation structures and equivalent circuit diagrams of the GTO, conventional RC-GTO (con-RC-GTO), and NF-RC-GTO, respectively. The SiC GTO is comprised of five layers: p-n-n-p-n, which functionally resemble two back-to-back PNP and NPN bipolar junction transistors (BJTs). The currents in these two BJTs are interdependent, and the device activates when the sum of the common-base current gains, denoted as αPNP and αPNP for the PNP and NPN BJTs, respectively, exceeds 1.
Compared to a standard GTO, both the conventional RC-GTO (con-RC-GTO) and the NF-RC-GTO feature an anode-shortened structure and a cathode-shortened structure, functioning as a reverse diode. In the equivalent circuit of a SiC RC-GTO, the additional connection to the N-drift region is modeled as a resistor (RL) placed parallel between the base and emitter terminals of the inherent PNP bipolar transistor (BJT). RL is nonlinear, primarily determined by the shape and doping concentration of the N-stop (and for NF-RC-GTO, also the N-float) regions.
During the initial phase of forward-conduction mode, the RC-GTO operates akin to an NPN BJT. This continues until the conduction current is sufficient to cause the voltage drop across RL to exceed 2.7 V, which is approximately the turn-on threshold voltage of a conventionally doped SiC PN junction at room temperature, fully activating the emitter-base junction of the inherent PNP transistor.
Once activated, the inherent PNP transistor contributes to conductivity modulation in the N-drift region, leading to a significant decrease in the resistance between the cathode and anode of the device. Subsequently, the RC-GTO transitions to operate as a conventional GTO. This shift from NPN BJT to GTO operation is marked by a voltage jump and an exponential increase in anode current, a process known as the snapback phenomenon.
Figure 1. Structures and equivalent circuit diagrams of the devices under study. (a) GTO; (b) conventional RC-GTO; (c) NF-RC-GTO.
To mitigate the snapback effect, the NF-RC-GTO incorporates an additional N-float layer with a lower doping concentration (such as 2 × 1014 cm−3). This layer boosts the lateral resistance above the P-injector, directing current flow through areas of higher resistance and enabling the emitter-base junction of the intrinsic PNP bipolar transistor to activate at much lower currents.
It is important to note the symmetrical relation of the cathode-shortened region to the gate structure in the NF-RC-GTO, which simplifies the formation of the cathode-shortened structure, especially when compared to traditional SiC-nGTO fabrication processes.
The performance of the various structures was simulated using Synopsys Sentaurus Technology Computer-Aided Design software, which computes fundamental physical partial differential equations and physical models, such as the Poisson equation and diffusion and transport equations, to facilitate the simulation of the structure and electrical characteristics of semiconductor devices.
Please note, all subsequent results are derived from simulation experiments. The basic physical models utilized in the TCAD simulations encompass impact ionization, incomplete ionization, Shockley–Read–Hall and Auger recombination, doping concentration-dependent carrier lifetime, and electric field and doping concentration-dependent carrier mobility.
The average lifetimes of carriers are defined as 2.5 µs for electrons and 0.5 µs for holes, which align with values commonly found in commercially available epitaxial layer structures. The standard parameters for the 13 kV SiC NF-RC-GTO, SiC con-RC-GTO, and con-GTO are compiled and presented in Table 1.
Table 1. Device parameters for simulations.
Figure 2 displays the current–voltage (I–V) characteristics for the GTO, con-RC-GTO, and NF-RC-GTO. In terms of forward turn-on performance, the conventional GTO exhibits optimal characteristics with a smooth transition, notably absent of any snapback effect.
For the RC-GTO variants, prior to the turn-on of the anode P/N diode, the devices exhibit behavior akin to an NPN BJT, a result of the additional electron excess provided by the N+ diode region. Specifically, in the case of the con-RC-GTO, a broader LG dimension diminishes the snapback effect. As LG widens from 110 μm to 120 μm, there is a notable reduction in the snapback voltage from 6.11 V down to 4.83 V.
Conversely, the NF-RC-GTO sees the complete elimination of the snapback effect with a reduced LG width of just 80 μm, affirming the effectiveness of the N-float structure in mitigating this issue. Furthermore, the forward conduction voltage drop (measured at a current density of 100 A/cm2) is comparable to that of the con-RC-GTO.
It is important to consider that an oversized LG dimension may lead to an uneven distribution of current within the device. This imbalance can result in thermal concentration issues, and additionally, it has the potential to diminish the available space for the reverse PN diode structure.
Figure 2. The current–voltage (I–V) characteristics of the GTO, con-RC-GTO, and NF-RC-GTO.
Figure 3 illustrates the initial paths of electron and hole currents during the conduction mode. Specifically, Figure 3a depicts the flow of electron current into the P-collector, bypassing the N-stop layer and entering the N-float layer in the NF-RC-IGBT under unipolar mode. This dual-layer structure effectively channels the current flow through the N-float region, significantly increasing the path resistance.
The current flow lines shown in Figure 3b confirm this. The voltage across the P-injector and N-float junction, distant from the N region, reaches at least 2.7 V at the earliest stage. Subsequently, the P-injector at this juncture begins to inject holes, facilitating conductivity modulation. Consequently, the device transitions into operating as a GTO.
Figure 3. (a) Current flow path; (b) current flow lines at the Anode side of the NF-RC-GTO in low current density mode.
The simple snapback model used for Figure 3a can be described as follows:
For the NF-RC-GTO, the N-float layer is pivotal in directing the current flow through areas of high resistance. This underscores the necessity for meticulous design of both the doping concentration and the geometry of the N-float region to more effectively suppress the snapback phenomenon.
3. Results
Figure 4 displays the characteristic curves of the forward off-state breakdown voltage. The breakdown voltages for the NF-RC-GTO, con-RC-GTO, and con-GTO are 15,303 V, 15,992 V, and 13,730 V, respectively. Both the NF-RC-GTO and con-RC-GTO, featuring an anode-short structure, exhibit higher breakdown voltages compared to the conventional GTO. Notably, the NF-RC-GTO shows an 11.4% improvement over the con-GTO.
This enhanced performance is attributed to the anode-short circuit structure, which allows leakage current from the reverse-biased junction to directly exit through the short-circuited anode. This mechanism also prevents hole injection at the P+ injector region, reducing the common-base current gain of the anode PNP BJT, thereby increasing the forward breakdown voltage. The slightly lower breakdown voltage of the NF-RC-GTO, compared to the con-RC-GTO, is due to the NF structure, which results in a shorter ndrift structure (104 µm).
Figure 4. BV curves of the con-GTO, con-RC-GTO, and NF-RC-GTO, respectively. The gate voltage is zero.
Figure 5 provides insight into the effect of doping concentration in the float region on the forward and reverse performance of NF-RC-GTOs, which are characterized by a consistent thickness of 4 μm and an LG length of 80 μm. The figure reveals that as the doping concentration decreases, the snapback voltage also reduces, and the snapback phenomenon completely vanishes at a doping concentration of 2 × 1014 cm−3.
This trend can be attributed to the increased lateral resistance above the P-injector resulting from the lower doping concentration, consequently leading to a reduced snapback voltage. Additionally, during the initial turn-on phase, the current in the NPN mode diminishes as the lateral resistance increases. It is also observed that with a higher doping concentration, the current handling capability slightly decreases. This is due to an increase in the compound current within the NF region, which negatively affects the hole injection efficiency in the anode region.
Figure 5. Forward and reverse conduction characteristics of the NF-RC-GTO with different N-float doping concentration (DF).
Figure 6 delineates the impact of the N-float structure’s thickness on the forward and reverse performance of NF-RC-GTOs. These devices share a consistent doping concentration and LG dimension for the N-float structure, at 2 × 1014 cm−3 and 80 μm, respectively.
The figure indicates that the snapback voltage decreases with an increase in the thickness of the N-float structure. Notably, the snapback phenomenon is eliminated when the thickness exceeds 3 μm. This effect can be attributed to the thicker N-float structure reducing the direct flow of NPN mode current through the N-stop region to the anode-short structure during the initial turn-on phase.
As a result, a higher proportion of electrons flow through the N-float region to the anode-short structure, facilitating earlier hole injection in the anode P-injector/N-float region. Furthermore, Figure 6 also reveals that variations in the thickness of the N-float structure within a certain range do not significantly affect the NF-RC-GTO’s forward and reverse high-current handling capability.
Figure 6. Forward and reverse conduction characteristics of the NF-RC-GTO with different thickness of N-float structure (TF).
The transient characteristics of the newly proposed NF-RC-GTO, with varying widths of the Anode-shortened structure (LD), are analyzed during the turn-off processes. A double pulse test (DPT) circuit is employed for evaluating the dynamic switching performance.
The DPT setup includes a high-voltage DC power supply of 8000 V, a gate resistor of 5 Ω, a clamped inductive load of 5 mH, and a gate signal of 15 V/−100 V to provide sufficient gate trigger current. At t = 0, the current in the inductor begins to increase from 0 at a rate of 1.6 A/µs. At t = 15 µs, the gate signal VG = 15 V is applied to trigger the turn-on of all GTOs, which lasts for 15 µs. At t = 30 µs, the gate signal switches to VG = −100 V to initiate the turn-off process.
Figure 7 displays the voltage and current waveforms of devices during the turn-off process, showcasing variations with different LD values in the DPT discharge circuits. The results show that the NF-RC-GTO surpasses the conventional GTO in the turn-off test.
This superior performance is attributed to the Anode-shortened structures of the NF-RC-GTO, which expedite the extraction of stored carriers, thus significantly accelerating the shutdown process. Additionally, for the NF-RC-GTO, a wider LD correlates with a shorter turn-off time. However, the turn-off time does not continue to decrease when LD exceeds 10 μm, as the carrier extraction path is already sufficiently wide at this point.
Figure 7. (a) Voltage and (b) current waveforms during turn-off process.
For the NF-RC-GTO, the device initially operates in BJT mode until the current reaches a level high enough to trigger the switch to GTO mode operation. This implies that the conductance modulation effect in the drift region is not fully activated, indicating that the concentration of injected non-equilibrium carriers in this region is lower than in conventional GTOs. Consequently, fewer carriers need to be extracted from the drift region during the turn-off process, resulting in a significantly reduced turn-off time compared to standard GTO devices.
Figure 8 displays the distribution of electron and hole concentrations in the drift region along the device’s vertical direction during normal turn-on at 15 A/cm2. The carrier concentration distribution for the NF-RC-GTO is observed to be in the range of 1 × 1016 cm−3, markedly lower than that of the con-GTO. This reduced carrier concentration is the fundamental reason behind the NF-RC-GTO’s rapid turn-off speed.
Therefore, the NF-RC-GTO possesses the potential for faster turn-off when the current to be switched off is not excessively high. The transition point from BJT to GTO mode in the device is indicated by a sudden increase in the slope of the IV curve.
Figure 8. Electron and hole density profiles in the drift region of con-GTO and NF-RC-GTO along the device’s vertical direction during normal turn-on at 15 A/cm2.
Generally, GTOs are characterized by stringent shutdown conditions and high turn-off losses. Figure 9 illustrates the correlation between the turn-off time and turn-off energy loss of the NF-RC-GTO and LD at 8000 V and 15 A/cm2, along with a comparison to traditional GTOs.
The figure indicates a decrease in both turn-off time and loss as the LD value increases. Notably, when LD exceeds 8 µm, there is a plateau in both turn-off time and loss, with minimal further changes observed. In comparison to standard GTOs, the turn-off time of the NF-RC-GTO is reduced by over 80%, and the turn-off loss is cut by more than 85%. These findings confirm the NF-RC-GTO’s enhanced capability in reducing both turn-off time and loss, particularly in operations involving lower currents.
Figure 9. Turn-off time and turn-off energy of NF-RC-GTO at different LD.
4. Conclusions
In summary, we have proposed a SiC NF-RC-GTO design, incorporating an N-float layer at the cell’s bottom. Experiments conducted with TCAD simulation software have shown that an optimal setting of the NF structure’s shape and doping concentration parameters can significantly reduce the snapback effect. When the thickness of the NF structure exceeds 4 µm and the doping concentration is set to 2 × 1014 cm−3, the snapback effect is completely eliminated.
Furthermore, the breakdown voltage of the proposed NF-RC-GTO has been improved by 11.4% compared to conventional GTOs. More importantly, at specific low current densities, it can reduce turn-off time by 80% and turn-off losses by 85%, indicating this design’s significant potential in reducing losses. Our next step in the research plan involves studying the thermal management capabilities of the NF-RC-GTO and investigating the manufacturing process flow of the NF-RC-GTO.
Authors
Chengcheng Wu ,Juntao Li, Zhiqiang Li, Lin Zhang, Kun Zhou, Xiaochuan Deng.
Original – MDPI
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STMicroelectronics announced a collaboration with Compuware Technology Inc, (Compuware), a leading provider of high-efficiency power supplies, on a reference design for server power using ST’s industry-leading silicon carbide (SiC), galvanic isolation, and microcontroller technologies. This reference design provides unparalleled power-supply options for digital power converter applications including server, datacenter and telecom power.
As demand for digital services continues to grow, fueled by Artificial Intelligence (AI), 5G, and the Internet of Things (IoT), keeping power usage under control is an important piece of the sustainability puzzle for data centers. The STDES-3KWTLCP reference design is perfect for a 3kW and higher wattage CRPS (Common Redundancy Power Supply) server power supply. This technical advancement comes with superior efficiency, faster switching, reduced energy losses, and better thermal management capabilities. In addition, this total system solution shortens time-to-market.
Compuware stands as a global power supply leader, holding the world record for the highest number of 80 PLUS Titanium certifications, ensuring unparalleled power efficiency. Engineered for excellence, Compuware power solutions are the ideal choice for HPC, AI, Deep Learning, Cloud, and advanced applications. With high power density, it optimizes space usage without compromising reliability and efficiency, setting a new performance standard in demanding computing environments.
“Combining ST’s latest SiC MOSFET, galvanic isolation, and microcontroller technologies with Compuware’s leading-edge power energy expertise is helping Compuware unleash our design creativity to develop high-density and -efficiency solutions. Now we can achieve 89W/in.3 power density, a small size, and high power output, this reference design is a great choice for power-hungry, high-performance computing applications,” according to Robin Cheng, Vice President at Compuware.
“With a focus on the Industrial market, ST’s Power & Energy Competence Center provides low-power, mid-power, and high-power solutions with the most advanced ST technologies to our customers, and this reference design- STDES-3KWTLCP can help our customers increase energy efficiency and reduce time-to-market using ST’s efficient and reliable power solutions,” said Eric Chou, Head of Power & Energy Competence Center at STMicroelectronics.
Original – STMicroelectronics
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Recently the European Space Agency (ESA) started its search for the technological advantage to improve their systems. Lead by research fellow Dr. Antxon Arrizabalaga, the project is aimed at studying the latest semiconductor technologies and exploring the impact they can have in the future of the space industry.
During its research, Dr. Antxon Arrizabalaga is looking forward to answer the following questions:
- Which are the next system-level figures the space power industry wants to achieve?
- Can the wide bandgap semiconductors help to achieve these figures?
- Which semiconductor ratings are demanded by the space power industry for each application?
At the moment the research project lead by Dr. Arrizabalaga is focusing on the silicon carbide (SiC) power semiconductor devices, as they are better suited for the requirements of the high-power applications. The team has already had several meetings with the main European space power companies discussing the points of interest mentioned above.
As a result, ESA received rich feedback with industry requirements and new ideas. And as anticipated, most of the companies are looking to the ways to increase power of their systems.
Thus, the following applications were mentioned the most:
- Latching current limiters (LCL) for high power distribution
- High-voltage (HV), increasing the traditional bus voltage, and high-power (HP) DC-DC converters
- Rectification and synchronous rectification
- HP motor drives
- Very HV applications, around and over 1 kV
Figure 1. The ratings of the semiconductor devices required by the industry for each application
According to Dr. Arrizabalaga, ESA classifies innovations in three categories, according to the degree of innovation they bring when compared to the state-of-the-art:
- Enhancing. It brings a substantial improvement to the state-of-the-art system.
- Based on a technology replacement
- For SiC devices it means replacing the Si devices in an existing application and optimizing the system to get system-level benefits
- Low risk, development time and cost for manufacturers
- Straightforward adoption by industry and high probability of success
- Enabling. It will allow a new feature, new application, or even a new mission.
- Critical technologies for a certain feature, application or mission
- For SiC devices it means that without the adoption of such devices, the new desired feature, application or mission is no longer possible
- Medium-high risk for manufacturers, higher development cost and effort, since it has never been done before
- More challenging adoption by industry, and lower probability of success
- Game-changing. It promises to bring entirely new capabilities (not considered for this study).
Figure 2. Classification of the applications mentioned by the industry and the main drivers needed to be optimized for each application.
The European Space Agency research team is looking forward to support the successful adoption of the wide bandgap (WBG) power semiconductor devices by the European space power industry, giving the European industry a competitive edge.
Original – Dr. Antxon Arrizabalaga
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Navitas Semiconductor announced its participation in the forthcoming 2024 Asia Charging Expo (ACE) in Shenzhen, China, from March 20th to 22nd, 2024. Visitors will explore the latest advances in GaN and SiC toward a fully-electrified “Planet Navitas” and the transition from fossil fuels.
Navitas will introduce the latest GaNFast™ and GeneSiC™ products to the audience in China for the first time, including: GaNSense™ half-bridge power ICs with application-specific features and higher power ratings, Gen-3 Fast SiC power FETs for high-power and higher-speed performance, and the world’s most protected GaN power devices – GaNSafe™.
Teaming up with UGREEN, Navitas will showcase a variety of UGREEN fast chargers featuring GaNFast power ICs, including the adorable and popular 30W and 65W Nexode Robot chargers, 100W Nexode Magsafe Charger Stand, and high-power 300W Nexode 5-port Desktop Charging Station. Many more GaNFast™ chargers will be displayed for visitors to experience the lightning speed of GaNFast charging.
Ye Hu, Navitas’ Technical Marketing Manager, will deliver a keynote presentation titled “A New Chapter in GaN: Navitas’ Integrated Drive and Loss-less Current Sensing GaNSense™ Half-bridge Solution” as part of the exposition’s World GaN Conference on March 22nd.
ACE 2024 will be held at Hall 6, Futian Convention and Exhibition Center, Shenzhen, China from March 20th to 22nd. Visitors to “Planet Navitas” (booth B57-B60) will meet experienced Navitas engineers to explore the power of next-gen power semiconductors for leading-edge applications. Navitas sales and distribution partners will also provide on-site support.
“The Asia Charging Expo is a critical event in the power electronics industry – gathering key experts from mobile, EV and industrial companies – and we are delighted to be part of it again to present our latest GaN and SiC technology,” said Charles Zha, VP and GM of Navitas China. “Our latest, advanced GaNFast and GeneSiC technologies bring revolutionary fast-charging capabilities to industry-leading Chinese customers.”
Original – Navitas Semiconductor
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Infineon Technologies AG introduced the new CoolSiC™ MOSFETs 2000 V in the TO-247PLUS-4-HCC package to meet designers’ demand for increased power density without compromising the system’s reliability even under demanding high voltage and switching frequency conditions.
The CoolSiC MOSFETs offer a higher DC link voltage so that the power can be increased without increasing the current. It is the first discrete silicon carbide device with a breakdown voltage of 2000 V on the market and comes in a TO-247PLUS-4-HCC package with a creepage distance of 14 mm and clearance distance of 5.4 mm. With low switching losses, the devices are ideal for solar (e.g. string inverters) as well as energy storage systems and electric vehicle charging applications.
The CoolSiC MOSFET 2000 V product family is ideally suited for high DC link systems with up to 1500 V DC. Compared to 1700 V SiC MOSFETs, the devices also provide a sufficiently high overvoltage margin for 1500 V DC systems. The CoolSiC MOSFETs deliver a benchmark gate threshold voltage of 4.5 V and are equipped with a robust body diode for hard commutation. Due to the .XT connection technology, the components offer first-class thermal performance. They are also highly resistant to humidity.
In addition to the CoolSiC MOSFETs 2000 V, Infineon will soon be launching the matching CoolSiC diodes: The first launch will be the 2000 V diode portfolio in the TO-247PLUS 4-pin package in the third quarter of 2024, followed by the 2000 V CoolSiC diode portfolio in the TO-247-2 package in the final quarter of 2024. These diodes are particularly suitable for solar applications. A matching gate driver portfolio is also available.
The CoolSiC MOSFET 2000 V product family is available now. In addition, Infineon also offers a suitable evaluation board: the EVAL-COOLSIC-2KVHCC. Developers can use the board as a precise universal test platform to evaluate all CoolSiC MOSFETs and diodes 2000 V and the EiceDRIVER™ Compact Single Channel Isolated Gate Driver 1ED31xx product family through double pulse or continuous PWM operation.
Original – Infineon Technologies
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Navitas Semiconductor announced their AI data center technology roadmap for up to 3x power increase to support similar exponential growth in AI power demands expected in just the next 12-18 months.
Traditional CPUs require typically only 300W and the data center ac/dc power supplies would typically power the equivalent of 10 of these or 3,000W (3kW). High-performance AI processors like NVIDIA’s ‘Grace Hopper’ H100 are already demanding 700W each today, with next-gen ‘Blackwell’ B100 & B200 chips anticipated to increase to 1,000W or more by next year.
To meet this exponential power increase, Navitas is developing server power platforms which rapidly increase from 3kW to up to 10kW. In August 2023, Navitas introduced a 3.2kW data center power platform utilizing latest GaN technology enabling over 100W/in3 and over 96.5% efficiency. Now, Navitas is releasing a 4.5kW platform enabled by a combination of GaN and SiC to push densities over 130W/in3 and efficiencies over 97%. These two platforms have already generated significant market interest with over 20 data center customer projects in development expected to drive millions in GaN or SiC revenues starting this year.
Today, Navitas also announces its plans to introduce an 8-10kW power platform by the end of 2024 to support 2025 AI power requirements. The platform will utilize newer GaN and SiC technologies and further advances in architecture to set all-new industry standards in power density, efficiency and time-to-market. Navitas is already engaged with major data-center customers, with full platform launch anticipated in Q4 ’24, completing this 3x increase in power demands in only 12-18 months.
Navitas’ unique data-center design center is creating these system designs to address the dramatic increases in AI data center power requirements, and assist customers to deploy platforms quickly and effectively to meet the accelerated time-to-market demands of rapid AI advances. System designs include complete design collateral with fully-tested hardware, schematics, bill-of-materials, layout, simulation and hardware test results to maximize first-time-right designs and fast revenue generation.
“The rapid development and deployment of artificial intelligence (AI) into global data centers has created a dramatic and unexpected power challenge for our entire industry,” noted Gene Sheridan, Navitas’ CEO and Co-Founder. “Our investment in leading-edge GaN and SiC technologies, combined with our unique data-center design center capabilities, have positioned us well. Our team has really stepped up to the challenge, with a 3x power increase in less than 18 months.”
Original – Navitas Semiconductor
