SiC Tag Archive

Abstract

A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (V_F) at I_S = 100 A/cm², which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (E_mox).

Additionally, the gate–drain capacitance (C_gd) and gate–drain charge (Q_gd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater R_on,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

1. Introduction

Nowadays, silicon carbide (SiC) is widely used in many applications because of its high critical electric field and superior thermal conductivity. The SiC MOSFET has a lower on-resistance and a faster switch speed compared with the Si-insulated Gate Bipolar Translator (IGBT). However, the body diode of the SiC MOSFET has a high on-state voltage drop of about 2–3 V because of its wide bandgap.

Additionally, when the body diode operates in bipolar mode, basal plane dislocations (BPDs) and stacking faults (SFs) are generated because of the recombination energy of the electrons and holes, and these faults cover most of the junction area and cause conduction losses to increase. Thus, the SiC MOSFET usually reverse-parallels a freewheeling diode to suppress the body diode; this extra diode not only increases the package size but also increases the parasitic inductance, which limits the switching frequency of the MOSFET.

One possible way of solving this problem is to integrate a unipolar diode into the MOSFET cell—in particular, a Schottky Barrier Diode (SBD)/Junction Barrier Controlled Schottky Diode (JBS). A disadvantage of these integrated unipolar diodes is the increased leakage current in the blocking state for the MOSFET. The use of a built-in channel diode is another option that can improve the reverse-recovery characteristics of the MOSFET, showing better switching characteristics, but the reliability problem caused by thin gate oxide still needs further research.

In recent research, low-barrier diodes (LBDs) have been adopted for their enhanced third-quadrant and switching performance in planar MOSFETs, but the planar structure limits the MOSFET’s usage in high-power applications because of its wide cell pitch and its high specificity of resistance (R_on,sp).

This paper proposes a 1200 V L-shaped split-gate trench SiC MOSFET integrated with a low-barrier diode. This structure can inhibit the reverse conduction of the body diode to avoid the effects of bipolar degradation and to extend the source to the bottom of the gate, forming a split gate to reduce the C_rss and to achieve a fast switching speed.

This study was carried out with numerical TCAD, and some essential models were included such as the Fermi–Dirac, incomplete-ionization, Shockley–Reed–Hall and Auger combination, Lombardi (CVT), impact-ionization, and band-narrowing models. A channel mobility of 50 cm²/(Vs) was used. The structure achieved a lower V_F, C_gd, and Q_gd and lower switching losses compared with a DT-MOS and a DT-MOS with an MOS-channel diode (DTC-MOS), and it also reduced the maximum oxide electric field (E_mox).

2. Device Structure and Mechanism

Figure 1 shows the schematic structures of the (a) DT-MOS, (b) DTC-MOS, and (c) proposed MOS. Based on the DTC-MOS, the proposed MOS turns part of the polysilicon gate to the source and extends to the bottom of the gate, forming an “L-shape” split gate. The gate-source connects to the source, so the overlap between the gate and drain decreases, which leads to a decrease in the C_gd. Meanwhile, at the right half-cell, the p-base turns into an n-base, so a low-barrier diode is integrated into this structure to improve its reverse conduction. The P-shield extends to the current spreading layer (CSL), and it decreases the E_mox in the blocking state and increases the BV, improving the device’s reliability.

Figure 1. Schematic cross-sectional structures of the (a) DT-MOS, (b) DTC-MOS, and (c) proposed MOSFET.

This device is based on a 4H-SiC, with the doping concentration and thickness of the N-drift set at 8 × 10¹⁵ cm⁻³ and 9 μm, respectively. The P-base region in all the devices had a doping concentration of 2 × 10¹⁷ cm⁻³ and a thickness of 0.5 μm. The N-base had a doping concentration of 3 × 10¹⁶ cm⁻³ and a thickness of 0.3 μm. The P-shield had a doping concentration of 2 × 10¹⁸ cm⁻³ and a thickness of 0.3 μm. The CSL had a doping concentration of 8 × 10¹⁶ cm⁻³ and a depth of 1.7 μm. The depth of the source trench and gate trench was 1.4 μm for both devices. The thickness of the gate oxide was 50 nm for both the N-base and P-base to improve the device reliability in the DT-MOS and proposed MOS. Considering the sufficient volume of the gate and the electric field, the distance of the oxide between the gate and gate-source and the thickness of the gate-source was 0.1 μm for the DTC-MOS and the proposed MOS. The cell pitch was 3.8 μm for the DT-MOS, and that of the other two devices was 4.2 μm. The main structure parameters of the DT-MOS, DTC-MOS, and proposed MOS are shown in Table 1.

Table 1. Structural parameters of the three devices.

Figure 2a shows the three-dimensional conduction band energy (E_C) distribution of the 4H-SiC in the proposed MOS structure at zero bias. The E_C decreased from the P-shield to the N-base at the right half-cell. The high doping of the P-shield and the low doping of the N-base led to a rapid depletion of the N-base region at zero bias, preventing the formation of a conducting channel. Therefore, there was no impact on the BV at low doping concentrations.

At zero bias, the E_C of the N-base was lower than the P-base, allowing electrons to overcome the potential barrier at a low V_ds. Figure 2b shows the E_C distribution along the a–a’ line (shown in Figure 1) at different V_ds. As V_ds decreased, the E_C increased in both the N-base and CSL. However, the E_C of the CSL increased faster than the N-base region. At V_ds = −1 V, the potential barrier became very low, allowing electrons to overcome the potential barrier, turning on the low barrier diode.

Figure 2. (a) Three-dimensional E_C distribution of the proposed MOSFET at zero bias (b–b’—the yellow dashed line in Figure 1). (b) E_C distribution of the SiO₂/SiC interface (a–a’—the red dashed line in Figure 1) at different V_ds.

The potential barrier model for LBD in a planar MOSFET is given by: 

where ϕ_{Si_SiC}and χ_{Si_SiC}are the work function and electron affinity difference between the Si and SiC. ɛ_OX and ɛ_SiC are the permittivity of the SiO₂ and SiC. N_Nb is the doping concentration of the N-base. The W_Nb is the width of the N-base. The structure of the low barrier diode in a planar structure and trench structure is the same, being formed by the N+ polysilicon, oxide, the low doping concentration N region, and the high doping concentration P region. Although the formula was obtained for planar structures, it is also applicable to trench structures.

The t_c is the thickness of the oxide between the gate-source and the N-base, which is fixed at 50 nm in the proposed MOS, as it has a great influence on device reliability. The t_c of the DTC-MOS was 20 nm, to easily turn on the built-in diode. From equation (1), N_Nb and W_Nb had an impact on the potential barrier of the LBD. Additionally, the thickness of the N-base (T_Nb) and the length of the P-shield (L_Psh) also influenced the resistance of the LBD, which in turn affects the V_F. Therefore, these parameters were optimized.

3. Simulation Results and Analysis

Figure 3a illustrates the impact of W_Nb and D_Nb on the BV and V_F. The solid circles represent BV values and the dashed circles represent V_F values. The W_Nb varied from 0.1 μm to 0.6 μm in steps of 0.1 μm. As W_Nb increased, the reverse current path expanded, which led to a decrease in V_F. However, the breakdown turned into a punch-through breakdown, which made the device unable to withstand high voltages.

With increasing D_Nb, the length of the potential barrier increased, leading to an increase in V_F. In this case, a longer W_Nb was required to trigger a punch-through breakdown. It is worth noting that when D_Nb exceeded 0.3 μm, the leakage current of the proposed MOS became comparable to the DT-MOS, which will be further discussed later. To tradeoff the BV, V_F, and leakage current, the optimal values of W_Nb = 0.3 μm and D_Nb = 0.3 μm were selected.

Figure 3. (a) Influence of D_Nb and W_Nb on BV and V_F; (b) BV, V_F at different L_Psh and N_Nb.

Figure 3b shows the tradeoff between the BV and V_F for the proposed MOS, considering different values of L_Psh and N_Nb. As the L_Psh increased from 1 μm to 1.5 μm in steps of 0.1 μm, the depletion region extended, leading to a decrease in E_mox and an increase in BV. However, the current path became narrow, leading to an increase in R_on,sp and V_F because of the change in the JFET resistance. With increasing N_Nb, the potential barrier of the low barrier diode reduced, leading to a decrease in V_F.

However, with high doping of N_Nb, the BV dropped below 1400 V, as shown for N_Nb = 3.5 × 10¹⁶ cm⁻³. At low N_N values_, the breakdown point occurred at the P-shield/N-drift junction, so the BV did not change with different N_Nb values. The change in N_Nb had no influence on R_on,sp. However, with increasing L_Psh, the R_on,sp increased from 1.84 mΩ × cm⁻² to 4.58 mΩ × cm⁻². In order to tradeoff BV, V_F, and R_on,sp, L_Psh = 1.3 μm and N_Nb = 3 × 10¹⁶ cm⁻³ were selected, represented by the red circle in Figure 3b.

The main parameters of the gate trench are shown in Figure 4a. The thickness of the gate trench was fixed at 1.4 μm. Figure 4b shows the influence of the distance between the gate and the gate-source (D_ox) on the C_gd and oxide electric field (E_ox). The voltage between the gate and the gate-source was set to 15 V. When D_ox was 0.1 μm for both the bottom and side wall of the gate, the E_ox was 1.5 MV/cm, which corresponds to the simulation results.

The thickness of the gate-source (T_GS) was fixed at 0.1 μm, and the thickness of gate poly (T_G) changed as D_ox increased or decreased. With increasing D_ox, the BV and V_F had no influence, so they are not included in Figure 4b. The D_ox has little influence on C_gd. Therefore, when D_ox was greater than 0.1 μm, E_ox was already less than 3 MV/cm. In order to facilitate subsequent simulations and ensure a sufficient volume of gate poly for adjusting the gate resistance, D_ox = 0.1 μm was selected.

Figure 4. (a) Parasitic capacitance for the C_gd of the proposed MOS. (b) Influence of device characteristics on the distance between the gate and gate-source (c) Influence of C_gd and R_on,sp on the thickness of the gate-source.

The influence of the device characteristics on T_GS is shown in Figure 4c; the D_ox was fixed at 0.1 μm. With increasing T_GS, there was no influence on BV and V_F, which is not shown in the figure. R_on,sp increased from 2.23 mΩ∙cm² to 2.28 mΩ∙cm², because the CSL, oxide, and gate poly formed an MIS structure, which increased the electron concentration of the CSL during conduction; this effect weakened as T_G decreased.

With increasing T_GS, C_gd decreases; this is because the gate-source extends to the bottom of the gate poly, resulting in a significant decrease in the overlap between the gate electrode and drain electrode. In this case, the C_gd can be expressed as:

As shown in Figure 4a, C_p is the oxide capacitance between the P-base and gate electrode, which is related to the thickness of the oxide and the overlap between the gate poly and the P-base. C_PN is the junction capacitance, which is completely independent of the gate parameters, and the C_PN decreases as V_ds increases. When increasing T_GS or D_ox, the T_G decreases, resulting in a decreased overlap between the gate poly and the P-base, thus causing a decrease in C_p.

Meanwhile, the T_G has no influence on C_PN, so the C_gd will decrease. However, it is worth noting that the C_gd is already sufficiently small, and further decreasing C_p cannot significantly change the C_gd. To ensure a suitable gate resistance for device, a sufficient volume of gate poly must be considered, which cannot be reflected in a simulation. Therefore, T_GS = 0.1 μm was selected for further simulations.

According to Figure 4b,c, the internal parameters of the gate trench have little influence on the performance of the device when the resistance of the gate poly is not considered; this shows that the proposed MOS has a wide process window for forming the L-shape gate-source.

Figure 5a shows the leakage current and blocking voltage for the three devices. The DT-MOS and proposed MOS blocking voltage exceeded 1400 V. However, the BV of the DTC-MOS was only 1340 V. This indicates that a wide cell pitch results in a decrease in the BV, while the extended P+ shield helps to improve the BV. For the proposed MOS, the leakage current increased faster at D_Nb = 0.2 μm.

However, when D_Nb = 0.3 μm, the BV was the same as D_Nb = 0.2 μm, the leakage current decreased to the level of the DT-MOS. This is because the leakage current is related to the parameters of the N-base before breakdown and the blocking voltage is related to the P-shield/N-drift junction, where the electric field is highest in the SiC region and avalanche breakdown occurs.

The electric field distribution of the three devices at 1200 V is shown in Figure 5b. The E_mox was located at the bottom of the oxide for all the devices. Compared with the DT-MOS and DTC-MOS, the proposed MOS had an extended P-shield, which was able to expand the depletion layer and provide better protection effects to the oxide. As a result, the E_mox was only 2.52 MV/cm, while the E_mox of the other devices was higher than 4 MV/cm.

With a high E_mox, a Fowler–Nordheim tunneling current may be generated; this carries electrons through the oxide layer, breaking the Si-O bond over time and generating defects, leading to a full breakdown of the SiO₂ layer, which has a great influence on device reliability.

Figure 5. (a) BV characteristics (b) electric field distributions with a drain bias at 1200 V of the DT-MOSF, DTC-MOS, and proposed MOS.

The I–V characteristic is shown in Figure 6a. In forward conduction, the R_on,sp of the DT-MOS and DTC-MOS was smaller than for the proposed MOS; this is because the DT-MOS has two channel paths for conduction, and because both DT-MOS and DTC-MOS do not extend the P-shield, which increases JFET resistance. With a low barrier diode, the V_F of the proposed MOS decreased significantly. The V_F was 2.85 V, 2.63 V, and 0.85 V at 100 A/cm² for the DT-MOS, DTC-MOS, and proposed MOS, respectively.

The current vector of the forward and reverse conduction is also shown in Figure 6a. It can be seen that there was only one current path for both conduction conditions. The current flows from the N+ region through the N-base to the drift region in reverse conduction, while the current flows from the drift region through the P-base to the N+ region in forward conduction. Figure 6b shows the hole concentration at I_s = 100 A/cm² of all the devices. In reverse conduction, the drift region of the DT-MOS obtained a high concentration of holes, which causes bipolar degradation.

Figure 6. (a) I–V characteristics of the three devices; (b) hole concentration distributions at I_s = 100 A/cm².

The short-circuit (SC) test results for the DT-MOS, DTC-MOS, and proposed MOS are shown in Figure 7. The SC test circuit used in the simulation is shown in Figure 7b. The bus voltage was 800 V. The stray inductance and resistance was 1 nH and 1 mΩ, respectively. The gate resistance was 10 Ω. A single pulse of 0 V/15 V gate bias was applied to the gate contact until the device failed due to thermal runaway caused by excessive temperatures.

The time from device turn-on to failure was 1.6 μs, 1.9 μs, and 2.8 μs for the DT-MOS, DTC-MOS, and proposed MOS, respectively. For the DT-MOS, the highest saturation current caused a faster temperature rise, leading to earlier device failure. Due to the single current channel and depletion layer extension of the P-shield region, the proposed MOS exhibited the lowest saturation current. As a result, the proposed MOS achieved the longest time until failure.

Figure 7. (a) Short circuit characteristics of the three devices; (b) short-circuit test circuit.

In the proposed MOS, the gate-source extended to the bottom of the gate, leading to a decrease in the overlap between the gate and the drain. As a result, the proposed MOS had the lowest C_gd compared to the DT-MOS and DTC-MOS, as shown in Figure 8a. While switching transients, the time constant is determined by the junction capacitance and gate resistors, which impact the switching speed of the devices. With a smaller capacitance, the devices switch at a faster speed.

The C_gd was 141.68 pF/cm², 136 pF/cm², and 1.81 pF/cm² for the DT-MOS, DTC-MOS, and proposed MOS, respectively. Figure 8b shows the gate charge for the three devices; the Q_gd of the DT-MOS was 569 nC/cm² and the Q_g (V_gs = 15 V) was 1467 nC/cm². The Q_gd of the DTC-MOS was 406 nC/cm² and the Q_g was 1136 nC/cm². However, the Q_gd of the LST-MOSFET was 6.7 nC/cm² and the Q_g was 333 nC/cm²; this result is consistent with the results for the C_gd, indicating that the proposed MOS can significantly reduce switching losses.

Figure 8. (a) C–V characteristics; (b) Gate Charge of three devices.

The switching waveforms and test circuit of the three devices are shown in Figure 9. Figure 9d shows the resistance switch circuit used in the simulation, with a load current of 10 A (100 A/cm²) at a normal current density. As can be seen in Figure 9a, the proposed MOS exhibited a lower Q_gd compared to the other devices. The miller plateau almost disappeared, leading to a faster transition of V_gs, which is consistent with the C_gd results. This characteristic resulted in a significantly faster switching speed for the proposed MOS compared to the other devices, thereby reducing switching losses.

From Figure 9b, the turn-on loss (E_on) and turn-off loss (E_off) of the DT-MOS was 0.28 mJ/cm² and 0.47 mJ/cm² and for the DTC-MOS was 0.26 mJ/cm² and 0.48 mJ/cm². However, for the proposed MOS, the E_on and E_off decreased to 0.09 mJ/cm² and 0.29 mJ/cm². The switching losses (E_SW) consisted of the E_on and E_off; the E_SW of the proposed MOS was 49.3% and 48.6% lower than that of the DT-MOS and DTC-MOS, respectively.

Figure 9. The switching waveforms of the DT-MOS, DTC-MOS, and Proposed MOS, respectively; (a) Turn-on and turn-off waveforms; (b) Turn-on loss and turn-off loss waveforms; (c) total power losses as a function of switching frequency f; (d) resistance switching circuit for simulations.

The total power losses (P_t) consist of conduction power losses and switching losses. When the device is operating under a square wave with a period T and a duty cycle D, the P_t can be expressed as (3):

When the device operated at 100 A/cm², the V_ds was 0.132 V, 0.156 V, and 0.223 V for the DT-MOS, DTC-MOS, and proposed MOS, which is consistent with the R_on,sp. The switching frequency, f, is related to the period, T, by the formula 

Although the R_on,sp of the proposed MOS was greater than that of the DT-MOS and DTC-MOS, the switching losses were the main contributor to power loss at high frequencies. Working at high frequencies can effectively reduce the total power losses of the device; it is worth it to increase the on-resistance slightly to achieve smaller switching losses at high frequencies. 

Figure 9c shows the total power loss as a function of f for the three devices, when a D of 50% was assumed. When the switching frequency was 50 KHz, the proposed MOS achieved the lowest power loss compared to the other devices due to its lower switching loss. At a switching frequency of 200 KHz, the P_t of the proposed MOS was 44.5% lower than the DT-MOS. With increasing f, the deference in P_t between the DT-MOS and the proposed MOS gradually increased.

The switching condition at a high current density (500 A/cm²) is shown in Figure 10. As the current density increased, both conduction losses and switching losses increased significantly. The E_SW of the three devices is shown in Figure 10a. The proposed MOS value was 0.96 mJ/cm², which was 42.9% and 36.4% lower than the DT-MOS and DTC-MOS.

However, the conduction losses of the proposed MOS increased faster than the other devices at 500 A/cm². As a result, the P_t of the proposed MOS was the highest before f = 200 KHz, as shown in Figure 10b. At a f of 250 KHz, the P_t of the proposed MOS was only 7.6% lower than that of the DT-MOS. Comparing the work conditions between a normal current density and a high current density, it is more favorable for the proposed MOS to work at a normal current density.

Figure 10. Device works at 500 A/cm²; (a) Turn-on loss and turn-off loss waveforms; (b) total power losses as a function of switching frequency f.

However, high switching speeds and frequencies may present a greater switching oscillation challenge. By adding RC snubbers, reducing the switching speed, or using active gate control techniques, the switching oscillation will be suppressed. However, the mentioned methods for suppressing switching oscillation will lead to an undesirable increase in switching time and switching losses.

There is a tradeoff between power losses and switching oscillation. An electronic structure that has transient part-time symmetry triggered by the switching-on and off of electronic devices can release oscillation energy, while still maintaining the very low loss state. This may be a good choice for suppressing switching oscillation in the future. The comprehensive performance of the three devices is shown in Table 2.

Table 2. Comparison of the three devices’ characteristics.

Figure 11 shows a possible process for the proposed MOS. The process starts with the formation of the P-shield region after epitaxy, as shown in Figure 11a. Then, the P-base and N-source are formed by ion implantation followed by high-temperature annealing, as shown in Figure 11b. After this, the gate trench is etched, the gate oxide is formed by chemical vapor deposition (CVD), and the polysilicon is deposited and etched to form the gate-source, which is shown in Figure 11c.

Then, the oxide is deposited and the N+ polysilicon is deposited and etched to form the gate electrode, which is shown in Figure 11d. Figure 11e shows the etching of the source trench and tilted implantation to form the P+ region along the sidewall of the source trench. Finally, Figure 11f shows the deposition of a passivation layer, the etching of the contact window, and the formation of the ohmic contact.

Figure 11. Key fabrication process flows for the proposed MOSFET: (a) Form P-shield layer. (b) Form P-base layer and N-source layer. (c) Etch to form gate trench and form oxide by CVD to form the gate oxide; deposit and etch polysilicon to form gate-source. (d) Deposit oxide and polysilicon to form gate. (e) Etch to form source trench and ion implantation to form the P+. (f) Form source electrode.

4. Conclusions

In this paper, a SiC novel MOSFET is proposed and studied by TCAD simulations. The proposed MOS integrates a low barrier diode and has a gate-source structure located under the bottom of gate. The simulation results demonstrate that the proposed MOSFET has a smaller V_F compared to the DT-MOS and DTC-MOS because of the low barrier diode, which suppresses the conduction of the body diode.

This allows the proposed MOS to operate under unipolar operations with reverse conduction, preventing the effects of bipolar degradation. The influence of the main parameters of LBD on device performance has been studied, and the optimal value has been determined. Additionally, the length of the P-shield has been studied to achieve a low E_mox and high blocking voltage. The parameters of the gate trench have also been studied, which show a high process tolerance for forming an L-shape without affecting the static performance.

In addition to the static performance, the C_gd and Q_gd of the three devices were compared. Due to a reduction in the overlap between the gate electrode and drain electrode, the proposed MOS achieved the lowest C_gd and Q_gd. As a result, the proposed MOSFET is able to achieve better switching speeds and lower switching losses.

The proposed MOS achieved the lowest total power losses under 50 KHz and higher switching frequencies with a normal current density. This indicates that the proposed MOSFET has more advantages in high frequency switching applications.

Authors

Yangjie Ou, Zhong Lan, Xiarong Hu, Dong Liu.

Original – MDPI