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Texas Instruments introduced two new power conversion device portfolios to help engineers achieve more power in smaller spaces, providing the highest power density at a lower cost. TI’s new 100V integrated gallium nitride (GaN) power stages feature thermally enhanced dual-side cooled package technology to simplify thermal designs and achieve the highest power density in mid-voltage applications at more than 1.5kW/in3.
TI’s new 1.5W isolated DC/DC modules with integrated transformers are the industry’s smallest and most power-dense, helping engineers shrink the isolated bias power-supply size in automotive and industrial systems by over 89%. Devices from both portfolios will be on display at this year’s Applied Power Electronics Conference (APEC), Feb. 25-29 in Long Beach, California.
“For power-supply designers, delivering more power in limited spaces will always be a critical design challenge,” said Kannan Soundarapandian, general manager of High Voltage Power at TI. “Take data centers, for example – if engineers can design power-dense server power-supply solutions, data centers can operate more efficiently to meet growing processing needs while also minimizing their environmental footprint. We’re excited to continue to push the limits of power management by offering innovations that help engineers deliver the highest power density, efficiency and thermal performance.”
Increase power density and efficiency with 100V integrated GaN power stages
With TI’s new 100V GaN power stages, LMG2100R044 and LMG3100R017, designers can reduce power-supply solution size for mid-voltage applications by more than 40% and achieve industry-leading power density of over 1.5kW/in3, enabled by GaN technology’s higher switching frequencies. The new portfolio also reduces switching power losses by 50% compared to silicon-based solutions, while achieving 98% or higher system efficiency given the lower output capacitance and lower gate-drive losses. In a solar inverter system, for example, higher density and efficiency enables the same panel to store and produce more power while decreasing the size of the overall microinverter system.A key enabler of the thermal performance in the 100V GaN portfolio is TI’s thermally enhanced dual-side cooled package. This technology enables more efficient heat removal from both sides of the device and offers improved thermal resistance compared to competing integrated GaN devices.
To learn more about the benefits of TI’s 100V GaN power stages for mid-voltage applications, read the technical article, “4 mid-voltage applications where GaN will transform electronic designs.”
Shrink bias power supplies by more than 89%
With over eight times higher power density than discrete solutions and three times higher power density than competing modules, TI’s new 1.5W isolated DC/DC modules deliver the highest output power and isolation capability (3kV) for automotive and industrial systems in a 4mm-by-5mm very thin small outline no-lead (VSON) package. With TI’s UCC33420-Q1 and UCC33420, designers can also easily meet stringent electromagnetic interference (EMI) requirements, such as Comité International Spécial des Perturbations Radioélectriques (CISPR) 32 and 25, with fewer components and a simple filter design.The new modules use TI’s next-generation integrated transformer technology, which eliminates the need for an external transformer in a bias supply design. The technology allows engineers to shrink solution size by more than 89% and reduce height by up to 75%, while cutting bill of materials by half compared to discrete solutions.
With the first automotive-qualified solution in this small package, designers can now reduce the footprint, weight and height of their bias supply solution for electric vehicle systems such as battery management systems. For space-constrained industrial power delivery in data centers, the new module enables designers to minimize printed circuit board area.
To learn more about the benefits of TI’s 1.5W isolated DC/DC modules, read the technical article, “How a new isolated DC/DC module can help solve power-density challenges.”
Pushing the limits of power at APEC 2024
These new devices are the latest ways TI is pushing power further and making innovation possible for engineers everywhere. At APEC 2024, TI will showcase the latest automotive and industrial designs for 48V automotive power; the first USB Power Delivery Extended Power Range full charging solution on the market; an 800V, 300kW silicon carbide-based traction inverter; high-efficiency power for server motherboards; and more.- Saturday, Feb. 24-Thursday, Feb. 29: Visit TI in the Long Beach Convention & Entertainment Center, Booth No. 1145. See TI.com/APEC for more information.
- Wednesday, Feb. 28 at 12 p.m. Pacific time: TI General Manager of Industrial Power Design Services Robert Taylor will present an industry session, “To Power Density and Beyond: Breaking Through Barriers to Achieve the Highest Power Density.” He will discuss innovations in packaging, integration and system-level techniques that are making greater power density possible.
- Throughout APEC: TI power experts will lead 20 industry and technical sessions to address power-management design challenges. The full schedule of TI experts’ industry and technical sessions is available at TI.com/APEC.
Original – Texas Instruments
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INDUSTRY PAPERS18 Min Read
Abstract
This paper aims to provide a guideline with respect to a reproducible thermal transient measurement for SiC MOSFETs. Although the thermal transient measurement based on sourcedrain voltage is a widely applied method for characterizing the thermal properties of MOSFETs, the approach developed for silicon-based devices may not be directly applicable to SiC devices. Therefore, this paper investigates the thermal transient measurement method for SiC MOSFETs using the source-drain voltage as the temperature-sensitive electrical parameter.
A comprehensive investigation of its linearity, sensitivity, and stability toward yielding the thermal structure-property of the device has been carried out. The investigation includes two primary characterization procedures: temperature calibration and cooling curve measurement. The associated key testing conditions, such as gate voltages, sensing and heating currents, etc., are covered. The study examines the impact of these conditions on both static and dynamic performance to provide a better understanding of the reproducible thermal transient measurement for SiC MOSFETs.
I. Introduction
Silicon carbide (SiC) MOSFETs are becoming increasingly popular in a wide range of applications, such as electric vehicles, industrial drives, and high-voltage transmissions. SiC offers several advantages over silicon, including lower power losses at higher switching frequencies, higher operating temperatures, and withstanding higher voltages. However, to ensure safe operation and maximize the device’s lifetime, all these superior performances must be achieved within the maximum junction temperature limit. Therefore, thermal characterization of SiC MOSFETs is essential to define the boundaries.
Thermal transient measurement is a widely accepted method to characterize the thermal properties of silicon (Si) power semiconductor devices. It has been recognized in several standards, such as JEDEC JESD 51-1 and JEDEC 51-14 and successfully applied to different applications over the past two decades, such as generating RC thermal models for electro-thermal simulation, packaging defect inspection, and junction-to-case thermal resistance measurement.
However, directly applying this approach to SiC MOSFETs is still doubtful to some extent. For instance, SiC MOSFETs do not have a pn junction in the forward direction and have low on-state resistance, which imposes challenges to measure transient thermal response by the channel voltage. Meanwhile, trapped charge carriers in the gate region may cause second-level electrical disturbances and inevitably affect the extraction of thermal transient from the coupled electrical disturbance. In the state-of-the-art, the source-drain voltage is one of the most used temperature sensitivity electrical parameters (TSEP) for SiC MOSFETs.
As shown in Fig. 1, the characterization consists of two major procedures, namely temperature calibration and cooling curve measurement. Improper selection of test conditions may result in misleading results. First, calibrating SiC MOSFETs for thermal transient measurement involves selecting the appropriate sensing current and gate voltage as step 1 shown in Fig. 1. While a sensing current of 1/1000 of the nominal current is commonly used for Si devices, it is however still under debate for SiC MOSFETs. Some studies use a small current below 1/1000 of the nominal current, while others suggest a much higher sensing current.
Additionally, selecting the appropriate negative gate voltage is critical for fully turning off the MOSFET channel and allowing all injected sensing current to flow through the body diode. However, the methodology for selecting the optimal gate voltage value and its impact on the transient thermal impedance remains unclear. It is worth noting that previous studies have mainly focused on steady-state calibration results, but transient temperature measurement requires consideration of transient behaviors, which has not been fully addressed in the literature. In addition to the calibration procedure, the cooling curve measurement of SiC MOSFETs involves other parameters such as heating currents and the switching transient of the gate state.
Previous studies have mainly focused on power cycling, where only the maximum and minimum temperature points are required. However, the investigation of thermal transient measurement with respect to the temperature dynamics across multiple time scales is limited. Electrical disturbances that occur at any point in time may lead to inaccurate thermal structure properties. Therefore, further investigation of the cooling curve measurement is also crucial. This paper comprehensively investigates the thermal transient measurement approach of SiC MOSFETs using Vsd as the TSEP and focuses on how to obtain more reproducible thermal structural information. Comparing to a preliminary conference version, the contributions of this article are three folds:
- Evaluated the impact of key testing conditions, including the gate turn-off voltage and sensing current, on the calibration based on static and dynamic tests. Three criteria are proposed to quantify the sensing current and two methods are proposed to justify the gate voltage.
- Investigated how various parameters affect cooling curve measurement in terms of static and dynamic responses.
- Derived a guideline of how to perform a reproducible thermal transient measurement of SiC MOSFETs with a proper selection of testing conditions and parameters.
II. Thermal Transient Measurement
Fig.1 illustrates the two major steps to perform the thermal transient measurement for a SiC MOSFET, namely, the temperature calibration and cooling curve measurement. The calibration is to obtain the relationship between the TSEP and the device temperature, which is controlled by an external system (e.g., an oven, a dielectric bath, or a temperature-controlled cooling plate). The MOSFET body diode pn junction voltage Vsd shows a linear temperature dependence given a small sensing current going through the device. By measuring Vsd under various temperatures, the relation of Vsd = f(T) can be calibrated.
Note that a low enough negative gate voltage has to be applied to completely shut the MOSFET channel off during this process (see Fig.2). In the second step, cooling curve measurement is carried out based on two current levels: one is the heating current (Iheat) to heat the device up, and the other is the sensing current for temperature monitoring with a negligible self-heating impact, as shown in Fig. 1 (Step 2).
Once Vsd is measured, the inversely calibrated T = f−1 (Vsd) in step 1 converts the measured voltage into the temperature. However, the temperature calibration is developed based on static conditions but the cooling curve is derived from dynamic voltage responses. The compatibility of the two steps has a prerequisite that the electrical disturbance is short and negligible. However, reference pointed out that SiC MOSFETs have much longer electrical disturbance compared to Si devices. Its impacts on thermal transient measurement are not fully understood and will be investigated in the following two sections.
III. Calibration: Impact of Sensing Current
To obtain reliable thermal transient measurement for SiC MOSFETs, the sensing current needs to be carefully selected to achieve good linearity, sensitivity, and low power dissipation. Additionally, to minimize unwanted electrical disturbances, a short sensing current pulse is preferable. In this section, three criteria are proposed to quantify the impacts of sensing current.
A. Impact of Sensing Current Density on Static Performance
1) Linearity: pn-junction voltage Vpn is used as TSEP due to its linear temperature dependence, which is given by
where Eg is band gap, q is the elementary charge, kb is Boltzmann constant, and A is a device-specific factor. These parameters are either independent of or have weak dependence on temperature. When a constant sensing current density jsense is applied, Vpn varies linearly with temperature T. However, for SiC MOSFETs, the voltage drops across the drift region, contact, and metallization can contribute significantly to Vsd when a high sensing current is used.
Moreover, at high temperatures and low current densities, the negative temperature coefficient of body diode results in a smaller Vpn. All above phenomenon can jeopardize the linear temperature dependence of Vsd and needs to be properly dealt. Fig. 3(a) shows the calibration results for different sensing currents ranging from 5 mA to 1000 mA. The proper selection of sensing current can be justified by the linearity between Vsd and temperature, which is further assessed by Pearson correlation coefficient ρlinear with 1 indicating perfect linearity
where cov denotes the covariance, and σ is the standard deviation. The left part of Table I lists that a sensing current of Isense = 100 mA gives the best linearity, whereas smaller and larger sensing currents result in a slightly worse performance.
2) Sensitivity: A viable TSEP sampling hardware requires a sensitivity SVT above 1 mV/K, which is defined asGiven a constant sensing current density, the temperature derivative of (1) yields
It indicates that when Vpn dominates the device’s voltage drop, the sensitivity decreases with the sensing current due to its negative logarithmic dependency in (4) and is also validated in the left part of Table I. All scenarios listed in the table meet the 1 mV/K requirement. Note that a higher or a lower SVT can also be selected according to the specific acquisition system.
3) Self Dissipation: To ensure accurate junction temperature measurement in the cooling phase, the self heating effect of the sensing current shall be negligible. A self-dissipation ratio is defined as
where Psense is the power dissipated by the sensing current which is generated by the measured TSEP voltage Vsd@Isense under Isense. Prate is the rated power dissipation of the tested device provided in datasheet. Generally, Prate can cause more than 100 ◦C junction temperature increase. ηsd ≤ 1% implies that the temperature increase by the sensing current is less than 1 ◦C (regarded as negligible here). Table I shows, except the cases of 500 mA and 1000 mA, all other scenarios meet the requirement of ηsd ≤ 1%.
B. Impact of Sensing Current Density on Dynamic Performance
During the period from 1 to 2 in Fig. 1, electrical and thermal transients occur simultaneously. This coupling poses challenge to extract the correct cooling curve of power devices. To address this issue, the standard JESD 51-1 introduces a delay time (tMD) to remove unwanted electrical transients plus a linear extrapolation to estimate the temperature at t = 0 s.
However, SiC MOSFETs are likely to suffer from long tMD, e.g., more than 600 µs under Isense = 5 mA in Fig. 3(b). It is much longer than the time scale of the chip’s thermal transient and hinders getting an accurate thermal structure property. However, by increasing Isense to 100 mA, tMD reduces to an acceptable 42 µs. Further increasing the sensing current has a limited effect on reducing tMD but rapidly increases the self-dissipation ratio.
Taking both static and dynamic performances into account, a sensing current of 100 mA achieves better overall performance for this study case.
IV. Calibration: Impact of Gate Voltage
A. Gate Turn-Off Voltage Selection
TCAD simulation in Fig. 4 shows that the electronic density changes dramatically in the channel region when the gate voltage varies from 0 V to -4 V but remains steady for a gate voltage less than -6 V to fully turn the channel off. This behavior is fundamentally different from Si devices, where a gate voltage of 0 V is sufficient as shown in Fig. 5(a).
Although existing studies have experimentally shown that Vgsoff = −6 V is enough to turn off the channel of SiC MOSFETs, it may not be applicable to all SiC MOSFETs due to different die designs and manufacturing processes. Different devices will be discussed in Section VI-C and the following part will focus on two methods for gate turn-off voltage selection.
1) Method 1 – Output Characteristic under Sensing Current: Output characteristic curves of body diode under the sensing current range can shift significantly from each other in case of insufficient gate voltages, such as Vgs = −3 V in Fig. 5(b) but start to overlap as the gate voltage approaches -6 V. To quantify this effects, an electrical conductance gdiode at the sensing current is defined as
When the entire current flows through the internal body diode, the conductance is independent of gate voltage and becomes a constant. The minimum Vgs ensuring a completely-off channel can then be identified by (7), for example, Vgs = −4.5 V for this case study as shown in Fig. 5(c).
2) Method 2 – Calibration Curves with Varied Gate Voltages: The calibration curves show the relationship between the sensing current and TSEP, and shall overlap with each other under various gate voltage provided a fully turned-off MOSFET channel. At the meantime, TSEP is linearly dependent on temperature. Therefore, similar to method 1, the criteria defined in (8) can be introduced to identify the minimum reasonable gate tun off voltage, which is a slightly different Vgs < −5 V than Vgs < −4.5 V as shown in Fig. 5(d).
B. Static and Dynamic Impacts of Gate Voltages
The calibration results under various gate voltage are also evaluated with respect to the linearity, sensitivity, and self-dissipation ratio. The measured results and its analytical summary are show in Fig. 5(d) and the right-hand side of Table I. When the gate voltage changes from 0 V to -3 V, the linearity deteriorates significantly compared to the other gate voltages. This poor linearity indicates that the measured Vsd is not primarily determined by the pn junction.
Moreover, by adjusting the gate turn-off voltage from 0 V to -8 V, the sensitivity and the self-dissipation ratio changes minorly. Regarding the dynamic behavior, the time delays under varied turn-on and turn-off gate voltages are investigated in Figs. 5(f) and (g), respectively. The effect of the gate voltage on the measurement delay time is almost negligible. Within the device’s maximum allowable gate voltage range, a lower gate turn-off voltage can improve the static behavior without significantly affecting the dynamic performance of the thermal transient measurement.
V. Cooling Curve Measurement
Once the calibration is completed, the established relationship between Vsd and temperature can be utilized for cooling curve measurements, where the selection and impacts of heating current, gate turn-on voltage etc. will be evaluated.
A. Impact of Sensing Current
Fig. 6(a) shows the cooling curves of a SiC MOSFET under same test conditions except the sensing current. Ideally, the two measurements shall overlap completely. However, the case with Isense = 5 mA takes 663 µs to reach the state 2 , comparing to only 42 µs under Isense = 100 mA. This is due to the fact that the body diode requires sufficient minority carrier charge accumulation to turn on, and it takes longer for a smaller sensing current.
The above measurements validate the dynamic study in Section III-B. Furthermore, the frequency analysis in Fig. 6(b) shows measurements with Isense = 5 mA exhibit large high-frequency noises, while it decays rapidly when Isense = 100 mA. At a certain bandwidth ∆f of the measurement, the noise can be modeled as a Johnson-Nyquist form, that is,
where Rpn is the resistance of the body diode at Isense, i.e., Rpn ≈ kbT /qIsense. It indicates that the noise in the measured voltage diminishes with the square root of the sensing current. Thus, a higher sensing current is advantageous for both shorter electric transients and lower noise.
B. Impact of Gate Turn-Off Voltage
Fig. 6 c) illustrates a series of cooling curves measured under various gate voltages. (Note that each cooling measurement shares the same gate voltage with its used calibration curve, which can be found in Table I). Abnormal temperature rises at approximately 2×10−4 s can be observed with severely insufficient gate voltages (e.g., 0 V and -1 V) but disappears with gate voltages less than -3 V.
This phenomenon is inconsistent with physical principles as the cooling stage does not involve any heat injection and therefore junction temperature rise shall not appear. Similar behavior is also observed with a conclusion of imperfect SiC MOSFET structure. Another reason for this inconsistency can be the insufficient gate turn-off voltage based on above findings. Moreover, temperature measurements go below the ambient temperature of 25 ◦C for voltages less than -3 V but turn normal by further lowering voltage to -6 V and beyond.
Similar effects can be observed in Fig. 6(d) where the thermal impedance curves, reflecting the thermal structure of a semiconductor package, remains unchanged until the sufficient enough gate voltage is applied. These inconsistencies underscore the significance of the gate turn-off voltage.
C. Impact of Gate Turn-On Voltage and Heating Current
Gate turn-on voltage decides the channel voltage drop in the heating stage. Together with the heating current, a higher power dissipation results in a higher junction temperature. A maximum temperature difference of up to 20 ◦C and 80 ◦C are observed in Fig. 6(e) and (g) for different Vgson and Iheat. The derived thermal impedance curves, however, barely change as shown in Fig. 6(f) and (h). Additionally, the measurement delay time remains unchanged. Thus, conclusion can be made that Vgson and Iheat have negligible affect on the thermal characterization given a sufficient gate turn-off voltage and sensing current.
VI. A Guideline for Reproducible Transient Thermal Measurements of SiC MOSFETs
A. Junction-to-Case Thermal Impedance MeasurementCooling curve measurement evaluates the thermal impedance from the device junction temperature to the ambient. More importantly, it can be used to identify the junction-to-case thermal impedance, which attracts more industrial interest. The JESD 51-14 standard clearly states the procedure by using transient dual interface approach. The overall principle is to conduct two transient thermal measurements of the identical device but with and without thermal interface material (denoted as tim and dry, respectively).
The two derived thermal curves start to separate as soon as the heat flow enters the TIM layer due to the surface roughness between package and cold-plate. Same procedure is followed in this paper based on the testing platform in Fig. 7(a) and previously identified test conditions of Vgs_off = -6 V and Isense = 100 mA. Subsequently, the cooling curves and thermal impedance curves are obtained as shown in Fig. 7(b) and (c). A clear separation point, or namely junction-to-case thermal impedance, can be observed at 0.8 K/W in Fig. 7(c) and in the thermal structure function curve in Fig. 7(d).
B. Transient Thermal Measurement Guideline
Based on the analysis and results discussed earlier, a flowchart to achieve a reproducible transient thermal measurement is provided in Fig. 8. It is evident that the gate turn-off voltage (Vgsoff) is a critical parameter that needs to be determined initially. Method 1 or 2 from Section IV-A can be applied. Certain margin can be added within the maximum gate voltage too as it benefits both static and dynamic states.
Subsequently, the sensing current (Isense) should be carefully selected. Too large or small sensing currents may not be conducive to accurate transient thermal measurements. It is important to ensure that the pn-junction dominates the measured drain-source voltage (Vsd) in terms of linearity, sensitivity, self-dissipation ratio, and measurement delay. Both the static and dynamic states should be evaluated comprehensively.
Once Vgsoff and Isense have been determined, the cooling curve measurement can be conducted accordingly. A final validation process can be added by varying the heating current (Iheat) or gate turn-on voltage (Vgsoff) to further validate the accuracy and reproducibility of the measurements.
C. Viability Validation
To validate the viability of the proposed flow, three additional devices from different vendors are tested with key information listed in Table II. Device 1 has been investigated in Section IV-V in detail. Fig. 9 shows the results of determining Vgsoff based on method 2. It is apparent that Vgsoff = −6 V, employed by multiple existing studies, is not sufficient enough for device 3 and 4 that require -10 V and -13 V to turn their channel off completely.
But it should be noted that these two values exceed the maximum allowable gate voltages according to devices data sheet. It implies that the current thermal transient measurement method based on Vsd may not be applicable to device 3 and 4 without exceeding the maximum gate turn-off voltage. Moreover, the selection of Isense with respect to the dynamic performance can be found in Fig. 9 together with the corresponding static performances listed in Table II. 100 mA is a proper sensing current for all 4 devices due to the short tMD and negligible self dissipation. It should be noted that the sensing current is around 5.26 ‰ of the rated current of the SiC MOSFET, which is different from Si devices.
VII. Conclusion
This paper investigates the thermal characterization of SiC MOSFET based on the body diode source-drain voltage. Two key steps, namely the calibration and cooling curve measurement, are evaluated comprehensively. The selection of key testing conditions, i.e., sensing/heating currents, gate turn-off/turn-on voltages, are thoroughly assessed based on their impacts on the thermal characterization and the following conclusions are achieved:
- Low enough gate turn-off voltage shall be used in both calibration and cooling curve measurement to ensure a completely shut channel and correct thermal impedance measurement. However, the required negative gate voltage may exceed the maximum allowable range, which causes the current thermal transient measurement method based on Vsd being not available for these devices within the maximum allowable gate voltage.
- Insufficient sensing current deteriorates the dynamics in terms of longer electrical disturbance and more noises, while too large sensing current sacrifices the steady-state performance in particular of a large self dissipation ratio.
- Gate turn-on voltage and heating current have negligible impacts on the measured thermal impedance. The consistency of the thermal impedance under varied gate turn-on voltage or heating current can be used as a validation.
Besides, a guide flowchart to perform reproducible transient thermal measurement for SiC MOSFETs is provided in this paper, which includes the selection of the electrical parameters and a validation process.
Authors
Yi Zhang, Yichi Zhang, Zhiliang Xu, Zhongxu Wang, Voon Hon Wong, Zhebie Lu, Antonio Caruso
Original – Research Gate
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EPC announced its participation in the premier power electronics conference, APEC 2024. The event, held from February 25 to February 29 in Long Beach, CA, brings together industry experts and thought leaders to explore the latest advancements in power electronics.
At APEC 2024, EPC highlights the industry’s most comprehensive portfolio of GaN-based power conversion solutions. With a focus on efficiency, reliability, and performance, EPC’s gallium nitride-based products offer unparalleled advantages for applications such as DC-DC converters, motor drives, and renewable energy.
Visit EPC at APEC 2024:
- Schedule a Meeting: Learn from GaN Experts and discover strategies to optimize your power systems. To schedule a meeting during APEC 2024 contact info@epc-co.com
- Exhibition Booth # 1045: Visit EPC’s booth to explore comprehensive portfolio of GaN-based solutions.
- Connect with EPC’s team of experts to gain insight into the ‘GaN First Time Right™ Design Process.
- Take the Change My Mind Challenge to see how EPC GaN FETs can be priced lower than equivalent silicon MOSFETs.
- Experience firsthand the superior performance and efficiency of EPC’s GaN products through live demonstrations including robotics, drones, and AI servers.
- Technical Presentations: Attend technical sessions to gain insights into the latest trends and advancements in GaN power conversion technology.
- Ultra-fast switching – the Fastest Power FETs in the Solar System
Industry Session (IS11.5): February 28 at 10:40 a.m.
Speaker: John Glaser, Ph.D. - Experimental Investigation on Transient Operation in Low-Voltage GaN FET Parallel Connection
Industry Session (IS16.4): February 28 at 2:45 p.m.
Speaker: Marco Palma - eGaN Integrated Circuits as a Building Block for Motor Drive Inverters
Industry Session (IS21.1): February 29 at 8:30 a.m.
Speaker: Marco Palma - Using Test-to-Fail Methodology to Accurately Project Lifetime of GaN HEMTs in Common DC-DC Converter Topologies
Industry Session (IS22.5): February 29 at 10:30 a.m.
Speaker: Shengke Zhang, Ph.D. - Emergence of Artificial Intelligence Requires GaN DC-DCs Highest Performance, Efficiency, and Density
Industry Session (IS27.1): February 29 at 1:30 p.m.
Speaker: Andrea Gorgerino
- Ultra-fast switching – the Fastest Power FETs in the Solar System
“At APEC 2024, we are excited to showcase our latest advancements in GaN technology, which empower our customers to achieve greater efficiency and performance in their applications,” said Nick Cataldo, VP of Sales and Marketing at EPC.
Original – Efficient Power Conversion
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Cambridge GaN Devices (CGD), the fabless, clean-tech semiconductor company that develops energy-efficient GaN-based power devices that make greener electronics possible, will be present at the upcoming APEC 2024, IEEE Applied Power Electronics Conference and Exposition. In addition to having its largest ever booth at the show, the company will contribute with a number of papers including an analysis of how GaN can play a part in supporting the exponential growth in power demanded by datacentres as the use of Artificial Intelligence (AI) proliferates.
GIORGIA LONGOBARDI | CHIEF EXECUTIVE OFFICER, CGD:
“With datacentres now demanding 100kW per rack and predicting even more in the very near future, power system designers are looking to employ GaN devices in new architectures. At CGD we are addressing this challenge with new devices and reference designs which we will be discussing at APEC, along with many other applications where GaN can play a huge role in enabling sustainable electronics solutions that are more efficient, have high performance and are more compact.”
CGD will present three papers at APEC:
- Tuesday 27th February, 15.00-15.30 – ‘How ICeGaN™ technology can address the datacentre challenges that digitalisation brings’, with Andrea Bricconi, Chief Commercial Officer, CGD and Peter Di Maso, VP of Business Development (Americas) CGD.
- Wednesday 28th February, 09.10-09.30 – ‘Evaluation of GaN HEMT dv/dt Immunity and dv/dt induced false turn-on energy loss’, with Nirmana Perera, Application Engineer, CGD.
- Thursday 29th February, 09:45 – 10:10: ‘Monolithic integration addresses the design challenges of GaN Power devices’, with Di Chen, Director of Business Development & Technical Marketing, CGD.
On booth 1553, CGD will present a range of demos designed to showcase industry’s first easy-to-use and scalable 650 V GaN HEMT family. ICeGaN™ H2 single-chip eMode HEMTs can be driven like a MOSFET, without the need for special gate drivers, complex and lossy driving circuits, negative voltage supply requirements or additional clamping components.
Addressing the increase in power required by server and industrial applications, CGD will show a 350 W PFC/LLC reference design using ICeGaN (650 V, 55 mΩ, H2 series). With a board power density of 23 W/in3, the bridgeless CrM Totem Pole PFC plus half-bridge LLC design has a peak efficiency of 95%, (93% average) and a no-load power consumption of 150 mW.
ANDREA BRICCONI | CHIEF COMMERCIAL OFFICER, CGD:
“GaN is now accepted as a reliable and proven technology that is able to deliver high efficiency and power density simultaneously. Datacentres, with their insatiable need for power, are an obvious application for GaN, but there are many other consumer, industrial and automotive applications where GaN can also demonstrate the ability to be a disruptive technology. CGD has delivered industry’s most easy-to-use GaN technology – ICeGaN – and we are keen to share our ideas with the audience at APEC.”
Original – Cambridge GaN Devices
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Micro Commercial Components unveiled 1700V SiC MOSFET – SICW400N170A-BP. Designed to elevate power conversion in a range of applications, this MOSFET features ultra-low on-resistance of only 400mΩ and high blocking voltage capability. SICW400N170A-BP SiC MOSFET enables high-speed switching while ensuring minimal conduction losses — essential requirements for optimizing frequency-dependent systems.
A standard, yet durable TO-247AB package delivers effective operation at a gate-source voltage of 20V with superior thermal stability and an operating junction temperature of +175°C.
This unwavering reliability in harsh conditions only adds to the component’s appeal and versatility for various high-voltage applications, including EV charging stations and renewable energy systems.
Features & Benefits:
- High blocking voltage capability (1700V)
- Ultra-low on-resistance (400mΩ) enhances efficiency
- Low capacitance enables faster switching
- Excellent thermal stability
- High operating junction temperature (to +175°C)
- Standard TO-247AB package
Original – Micro Commercial Components
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GaN / LATEST NEWS / PRODUCT & TECHNOLOGY / WBG2 Min Read
Innoscience Technology has launched a new 100V bi-directional member of the company’s VGaN IC family. The first family of VGaN devices rated 40V with wide on-resistance range (1.2mOhm – 12mOhm) have been successfully deployed in the USB OVP of mobile phones such as OPPO, OnePlus etc.
The new 100V VGaN (INV100FQ030A) can be employed to achieve high efficiency in 48V or 60V battery management systems (BMS), as well as for high-side load switch applications in bidirectional converters, switching circuits in power systems, and other fields. Such device it is ideal in application such as home batteries, portable charging station, e-scooters, e-bikes etc.
One VGaN replaces two back-to-back Si MOSFETs; they are connected with a common drain to achieve bidirectional switching of battery charging and discharging, further reducing on-resistance and loss significantly with respect to traditional Silicon solution. BOM count, PCB space and costs are also reduced accordingly.
The INV100FQ030A 100V VGaN IC supports two-way pass-through, two-way cut-off and no-reverse-recovery modes of operation. Devices feature an extremely low gate charge of just 90nC, ultra-low dynamic on-resistance of 3.2mΩ and small, 4x6mm package size.
Dr. Denis Marcon, General Manager, Innoscience Europe comments: “Innoscience’s continuous innovation and development of our core technology plus our 8-inch wafer GaN IDM model will accelerate the miniaturization of systems, making them more efficient and energy-saving.”
Innoscience ‘s 100V GaN series products are in mass production in En-FCQFN (exposed top side cooling) and FCQFN packaging.
Original – Innoscience Technology
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GaN / LATEST NEWS / WBG2 Min Read
Infineon Technologies AG announced a collaboration with Worksport. Worksport Ltd. will use Infineon’s GaN power semiconductors GS-065-060-5-B-A in the converters for its portable power stations to increase efficiency and power density. Enabled by Infineon’s GaN transistors, the power converters will be lighter and smaller in size with reduced system costs. In addition, Infineon will support Worksport in the optimization of circuits and layout design to further reduce size and increase power density.
“Infineon’s high-quality standard and solid supply chain provide us with the best components to ensure power-dense converters for our COR system product line and contribute to a first-class end product performance,” said Worksport CEO Steven Rossi.
The company’s COR battery system can be integrated into a pickup truck or recharged by any solar panel or wall outlet. By replacing the former silicon switch in the power converter with Infineon’s GaN power semiconductors and operating the transistors at higher switching frequency, Worksport will be able to reduce the battery system weight by 33 percent and system costs by up to 25 percent.
The working relationship with Infineon will also help Worksport to reduce CO2 in the manufacturing process. GaN is proving itself as a game-changing technology across many markets and applications. For example, in data centers, GaN solutions have a global energy savings potential of 21 TWh annually, 10 million tons of Carbon Dioxide (CO2) equivalent.
“In order to further drive electrification and decarbonization, the industry’s power designs require innovation,” said Johannes Schoiswohl, Business Line Head GaN Systems of Infineon’s Power & Sensor Systems Division. “With our GaN power semiconductors we enable Worksport to create the next generation portable power stations that users require.”
Infineon’s GS-065-060-5-B-A is an Automotive-grade 650 V enhancement mode GaN-on-Silicon power transistor. It offers very low junction-to-case thermal resistance for demanding high power applications such as on-board chargers, industrial motor drives and solar inverters. Furthermore, it features simple gate drive requirements (0 V to 6 V) and a transient tolerant gate drive (-20 / +10 V).
Original – Infineon Technologies